Отправлено axalay 08 декабря 2003 г. 11:01 В ответ на: Массивы памяти в максплюсе на VerilogHDL отправлено Mroot 05 декабря 2003 г. 16:10

module RAM (
data,
wraddress,
rdaddress,
wren,
wrclock,
rdclock,
q);

input [15:0] data;
input [3:0] wraddress;
input [3:0] rdaddress;
input wren;
input wrclock;
input rdclock;
output [15:0] q;

wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];

lpm_ram_dp lpm_ram_dp_component (
.rdclock (rdclock),
.wren (wren),
.wrclock (wrclock),
.data (data),
.rdaddress (rdaddress),
.wraddress (wraddress),
.q (sub_wire0));
defparam
lpm_ram_dp_component.lpm_width = 16,
lpm_ram_dp_component.lpm_widthad = 4,
lpm_ram_dp_component.lpm_indata = "REGISTERED",
lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
lpm_ram_dp_component.lpm_rdaddress_control = "REGISTERED",
lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dp_component.lpm_hint = "USE_EAB=ON";

endmodule //RAM

• Ответ: — Mroot   (15.12.2003 11:02, 168 байт)