[an error occurred while processing this directive]
|
//------------- top module
`define KEY_REG_ADDR 8'h88
`define ROM_BAR_ADDR 8'h30
module prim_bkend2(LA, BE, data_tran,
cfg_sel, dma_sel, mem_sel, cfg_sel,
io_sel0, io_sel1, io_sel2, io_sel3,
p2p_en_, test, ide_sel, fifo_sel,
p2p_reg_sel, key_reg_sel, p2p_rom_sel,
hdd_, rom_, ide_16bit_
);
//input signals
input [7:0] LA;
input [3:0] BE;
input data_tran;
input cfg_sel;
input io_sel0;
input io_sel1;
input io_sel2;
input io_sel3;
input dma_sel;
input mem_sel;
input p2p_en_;
input test;
//output signals
output ide_sel;
output fifo_sel;
output p2p_reg_sel;
output key_reg_sel;
output p2p_rom_sel;
output hdd_;
output rom_;
output ide_16bit_;
//------------------------- Equations ------------------------------//
prim_addr_decoder addr_decoder (
.LA(LA[7:0]),
.BE(BE[3:0]),
.data_tran(data_tran),
.io_sel0(io_sel0),
.io_sel1(io_sel1),
.io_sel2(io_sel2),
.io_sel3(io_sel3),
.dma_sel(dma_sel),
.mem_sel(mem_sel),
.cfg_sel(cfg_sel),
.p2p_en_(p2p_en_),
.test(test),
.ide_sel(ide_sel),
.fifo_sel(fifo_sel),
.p2p_reg_sel(p2p_reg_sel),
.key_reg_sel(key_reg_sel),
.p2p_rom_sel(p2p_rom_sel),
.hdd_(hdd_),
.rom_(rom_),
.ide_16bit_(ide_16bit_)
);
endmodule
//----------------- low level module
`define KEY_REG_ADDR 8'h88
`define ROM_BAR_ADDR 8'h30
module prim_addr_decoder(LA, BE, data_tran,
cfg_sel, dma_sel, mem_sel, cfg_sel,
io_sel0, io_sel1, io_sel2, io_sel3,
p2p_en_, test, ide_sel, fifo_sel,
p2p_reg_sel, key_reg_sel, p2p_rom_sel,
hdd_, rom_, ide_16bit_
);
//input signals
input [7:0] LA;
input [3:0] BE;
input data_tran;
input cfg_sel;
input io_sel0;
input io_sel1;
input io_sel2;
input io_sel3;
input dma_sel;
input mem_sel;
input p2p_en_;
input test;
//output signals
output ide_sel;
output fifo_sel;
output p2p_reg_sel;
output key_reg_sel;
output p2p_rom_sel;
output hdd_;
output rom_;
output ide_16bit_;
// internal resources and signals
wire p2p_rom_bar;
wire ide_rom_sel;
wire ide_cfg_sel;
wire ide_cs_sel;
wire ide_as_sel;
//------------------------- Equations ------------------------------//
assign p2p_rom_bar = (cfg_sel && (LA[7:0]==`ROM_BAR_ADDR)
&& ~p2p_en_) ? 1:0;
assign p2p_reg_sel = ((cfg_sel & ~p2p_en_ & LA[7]) | p2p_rom_bar) ? 1:0;
assign key_reg_sel = (cfg_sel && ~p2p_en_
&& (LA[7:0]==`KEY_REG_ADDR)) ? 1:0;
assign p2p_rom_sel = (mem_sel & ~p2p_en_) ? 1:0;
assign ide_rom_sel = (mem_sel & p2p_en_) ? 1:0;
assign ide_cfg_sel = ((cfg_sel & p2p_en_) |
(cfg_sel & ~p2p_en_ & ~LA[7] & ~p2p_rom_bar)) ? 1:0;
assign ide_cs_sel = (io_sel0 | io_sel2) ? 1:0;
assign ide_as_sel = (io_sel1 | io_sel3) ? 1:0;
assign fifo_sel = (ide_cs_sel && (LA[2:0] == 3'b000)) ? 1:0;
assign ide_sel = ((ide_cs_sel && (LA[2:0] != 3'b000))
| ide_as_sel | dma_sel | ide_cfg_sel | ide_rom_sel) ? 1:0;
assign hdd_ = (((ide_sel | fifo_sel) && data_tran) || test) ? 0:1;
assign rom_ = ((p2p_rom_sel && data_tran) || test) ? 0:1;
assign ide_16bit_ = ((fifo_sel && data_tran
&& (BE[3:0]==4'b1100)) || test) ? 0:1;
endmodule
//---- Sinthesis report (WebPack 4.2)
Release 4.2WP0.x - xst E.35
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.49 s | Elapsed : 0.00 / 0.00 s
--> Parameter overwrite set to YES
CPU : 0.00 / 0.49 s | Elapsed : 0.00 / 0.00 s
--> =========================================================================
---- Source Parameters
Input Format : VERILOG
Input File Name : prim_bkend2.prj
Verilog Search Path : ./testbench
Verilog Include Directory : ./testbench
---- Target Parameters
Target Device : XBR
Output File Name : prim_bkend2
Output Format : NGC
Target Technology : xbr
---- Source Options
Top Module Name : prim_bkend2
Automatic FSM Extraction : YES
FSM Encoding Algorithm : User
FSM Flip-Flop Type : D
Mux Extraction : YES
Resource Sharing : NO
Complex Clock Enable Extraction : YES
---- Target Options
Add IO Buffers : YES
Equivalent register Removal : YES
Macro Generator : Macro+
MACRO Preserve : YES
XOR Preserve : YES
---- General Options
Optimization Criterion : Speed
Optimization Effort : 1
Check Attribute Syntax : YES
Keep Hierarchy : YES
---- Other Options
Clock Enable : NO
wysiwyg : YES
=========================================================================
Setting FSM Encoding Algorithm to : User
Synthesizing Unit ========================================================================= Found no macro Optimizing unit Optimizing unit Merging netlists... WARNING:Xst:615 - Net ide_cfg_sel not found, property SOURCE_NODE not attached. Design Statistics =========================================================================
E-mail:
info@telesys.ru
Compiling source file : prim_bkend2.prj
Compiling included source file 'prim_addr_decoder.v'
Module
Continuing compilation of source file 'prim_bkend2.prj'
Compiling included source file 'prim_bkend2.v'
Module
Continuing compilation of source file 'prim_bkend2.prj'
Compiling included source file 'D:/Xilinx/Webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'prim_bkend2.prj'
No errors in compilation
Analysis of file
Starting Verilog synthesis.
Analyzing module
Module
Set user-defined property "SOURCE_NODE = yes" for signal
Set user-defined property "SOURCE_NODE = yes" for signal
Set user-defined property "SOURCE_NODE = yes" for signal
Set user-defined property "SOURCE_NODE = yes" for signal
Set user-defined property "SOURCE_NODE = yes" for signal
Analyzing top module
WARNING:Xst:852 - prim_bkend2.v (Line 65). Unconnected input port 'cfg_sel' of instance 'addr_decoder' is tied to GND.
Module
Related source file is prim_addr_decoder.v.
WARNING:Xst:646 - Signal
WARNING:Xst:646 - Signal
WARNING:Xst:647 - Input
WARNING:Xst:647 - Input
WARNING:Xst:647 - Input
WARNING:Xst:647 - Input
WARNING:Xst:647 - Input
WARNING:Xst:647 - Input
Unit
Synthesizing Unit
Related source file is prim_bkend2.v.
Unit
HDL Synthesis Report
=========================================================================
Starting low level synthesis...
implementation constraint: SOURCE_NODE : ide_as_sel
implementation constraint: SOURCE_NODE : ide_cfg_sel
implementation constraint: SOURCE_NODE : ide_cs_sel
implementation constraint: SOURCE_NODE : ide_rom_sel
implementation constraint: SOURCE_NODE : p2p_rom_bar
ERROR:Xst:269 - Redeclaration of a connector name : cfg_sel.
WARNING:Xst:615 - Net p2p_rom_bar not found, property SOURCE_NODE not attached.
=========================================================================
Final Results
Output File Name : prim_bkend2
Output Format : NGC
Optimization Criterion : Speed
Target Technology : xbr
Keep Hierarchy : YES
Macro Preserve : YES
Macro Generation : Macro+
XOR Preserve : YES
# Edif Instances : 60
# I/Os : 30
CPU : 1.27 / 1.76 s | Elapsed : 1.00 / 1.00 s
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