|
module c (CLK,RST,DATA);
input CLK,RST;
output DATA;
reg [31:0] DATA;
always @(posedge CLK or posedge RST)
DATA = RST ? 0 : (DATA + 1);
endmodule
результат MAX+
** DEVICE SUMMARY **
Chip/ Input Output Bidir LCs
POF Device Pins Pins Pins LCs % Utilized
c epf6016qc208-2 2 32 0 32 2 %
User Pins: 2 32 0
E-mail: 
info@telesys.ru
