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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
----
----
constant adr_control : integer := conv_integer(unsigned("1111111111"));
----
----
process(CLK)
begin
if CLK'event and CLK='1' then
if WR='1' then
case conv_integer(unsigned(ADR)) is
when adr_control => ADC_EN <= DI(0);
-- здесь ошибка
when others => null;
end case;
end if;
end if;
end process;
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