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написал вот такой код в A-HDL, всё работает при симуляции. После синтеза в LeonardoSpectrum, MAX Plus в симуляции показывает на выходе undefine :-(
кто виноват ???
вот собственно код:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity freq_div is
port(
CLK : in STD_LOGIC;
DIV : in STD_LOGIC_VECTOR(2 downto 0);
WR : in STD_LOGIC;
CS : in STD_LOGIC;
CLK_DIV : out STD_LOGIC
);
end freq_div;
architecture freq_div of freq_div is
signal cnt : std_logic_vector(7 downto 0) := "00000000";
signal DIV_N: std_logic_vector(2 downto 0):= "000";
begin
process(CS, WR, CLK)
begin
if (rising_edge(CLK)) then
cnt <= cnt + "1";
end if;
if CS = '0' and WR = '0' then DIV_N <= DIV;
end if;
case DIV_N is
when "000" => CLK_DIV<= CLK; -- /1
when "001" => CLK_DIV<= cnt(0); -- /2
when "010" => CLK_DIV<= cnt(1); -- /4
when "011" => CLK_DIV<= cnt(2); -- /8
when "100" => CLK_DIV<= cnt(3); -- /16
when "101" => CLK_DIV<= cnt(4); -- /32
when "110" => CLK_DIV<= cnt(5); -- /64
when "111" => CLK_DIV<= cnt(6); -- /128
when others => null;
end case;
end process;
end freq_div;
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