Отправлено Victor® 10 сентября 2003 г. 17:12 В ответ на: делитель частоты VHDL отправлено Bug 08 сентября 2003 г. 18:29

TITLE "Synchronous Divisor by N with 50/50 Output Duty Cycle";
-- MAIN PROJECT: For Internal Purposes
-- AUTHOR NAME : Victor Levandovsky
-- COMPANY NAME: Electronic Systems
-- DATE : 17.11.2001
-- REV. NUMBER : 1
-- NAME OF PREVIOUS REVISION PROJECT: NONE
-- DIFFERENCIES FROM PREVIOUS REVISION: NONE

PARAMETERS (DIVISOR =171);
CONSTANT WIDTH = CEIL(LOG2(DIVISOR));
CONSTANT DURATION = CEIL(DIVISOR DIV 2);

SUBDESIGN Ndiv_v1
(
clk :INPUT; -- Input Clock
res/ :INPUT = VCC; -- Asynch. Reset (Active LOW)
clk_ena :INPUT; -- Clock Enable (Active HIGH)
div_n :OUTPUT; -- Output Clock w. 50/50 Duty Cycle (CLK/N)

)
VARIABLE
flop_r[WIDTH-1..0] :DFFE;
flop_f[WIDTH-1..0] :DFFE;
comp_r :NODE;
comp_f :NODE;
illegal_correct_r :NODE;
illegal_correct_f :NODE;
wave_r :NODE;
wave_f :NODE;

BEGIN

---------------------- Rising Edge Counter with Modulus equal to DIVISOR ------------

-- Condition for Synch. Load DFFE`s with Zero
comp_r = (flop_r[] == (DIVISOR - 1));

-- Illegal States Correction
illegal_correct_r = (flop_r[] >= DIVISOR);

-- Counter Description
flop_r[].clk = clk;
flop_r[].clrn = res/;
flop_r[].ena = clk_ena;

IF comp_r OR illegal_correct_r OR illegal_correct_f THEN
flop_r[].d = GND;
ELSE
flop_r[].d = flop_r[].q + 1;
END IF;

---------------------- Falling Edge Counter with Modulus equal to DIVISOR -----------

-- Condition for Synch. Load DFFE`s with Zero
comp_f = (flop_f[] == (DIVISOR - 1));

-- Illegal States Correction
illegal_correct_f = (flop_f[] >= DIVISOR);

-- Counter Description
flop_f[].clk = !clk;
flop_f[].clrn = res/;
flop_f[].ena = clk_ena;

IF comp_f OR illegal_correct_r OR illegal_correct_f THEN
flop_f[].d = GND;
ELSE
flop_f[].d = flop_f[].q + 1;
END IF;

----------------------- TEST Outputs for Simulation ---------------------------------

wave_r = (flop_r[] < DURATION);
wave_f = (flop_f[] < DURATION);

----------------------- Primary Output ----------------------------------------------

div_n = wave_r & wave_f;

----------------------- Insert Additional Information -------------------------------

ASSERT
REPORT "Designed by V. Levandovsky, Copyright © 2001 Electronic Systems"
SEVERITY INFO;
ASSERT
REPORT "Used % DFFE`s for Internal Counters" WIDTH * 2
SEVERITY INFO;
END;