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architecture Struct of m_seq is
signal PRN_REG : std_logic_vector(LENGTH-1 downto 0);
signal PRN_REG_next : std_logic_vector(LENGTH-1 downto 0);-- purpose: convolution XOR
function BIT_CONV_XOR (
inp : std_logic_vector)
return std_logic is
variable res : std_logic := '0';
variable cnt : integer;
begin -- BIT_CONV_XOR
for cnt in inp'range loop
res := res xor inp(cnt);
end loop; -- cnt
return res;
end BIT_CONV_XOR;begin
PRN_REG_next <= BIT_CONV_XOR(PRN_REG and MASK) & PRN_REG(PRN_REG'length-1 downto 1);
m_reg : process (CLK)
begin
if (CLK'event and CLK = '1') thenreg : if ENA = '0' then
PRN_REG <= not conv_std_logic_vector(0, PRN_REG'length);
else
PRN_REG <= PRN_REG_next;
end if reg;
end if;end process m_reg;
end Struct;
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