Отправлено MemoryTest 05 августа 2003 г. 09:58

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adress_compare is

generic( ADRESS_LENGTH: INTEGER :=10);

Port
(
input_adress: in STD_LOGIC_VECTOR (ADRESS_LENGTH-1 downto 0);
subreg0_select: out STD_LOGIC;
subreg1_select: out STD_LOGIC
);
end adress_compare;

architecture Behavioral of adress_compare is

constant SUBREG0_ADRESS: STD_LOGIC_VECTOR (ADRESS_LENGTH-1 downto 0):=X"360";
constant SUBREG1_ADRESS: STD_LOGIC_VECTOR (ADRESS_LENGTH-1 downto 0):=X"361";

begin
main_process:
process(input_adress)
begin
case (input_adress) is

when SUBREG0_ADRESS => subreg0_select<='1';
when SUBREG1_ADRESS => subreg1_select<='1';

when others => subreg0_select<='0';
subreg1_select<='0';

end case;
end process; -- main_process

end Behavioral;

ругается следующими словами:
ERROR:HDLParsers:839 - C:/Xilinx_WebPack/bin/adress_comapare.vhd Line 34. Selector (Signal 'input_adress' of type std_logic_vector) is an unconstrained array.
-->

• Посмотрел — Leoyv   (05.08.2003 13:10, 1410 байт)
  • Большое спасибо. Скачал седня туториал еще у aldec- а по VHDL, поштудирую на досуге. — MemoryTest   (05.08.2003 13:27, пустое)