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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnts7 is
port(sr, clk, clk_en : in std_logic;
term_cnt : inout std_logic);
end;
architecture behavior of cnts7 is
begin
process (sr, clk, clk_en)
variable q_out: std_logic_vector(2 downto 0);
begin
if (clk = '1' and clk'event) then
if sr = '1' then
q_out := "000";
elsif (clk_en = '1') then
-- if q_out = "110" then
if term_cnt = '1' then
q_out := "000";
else
q_out := q_out + "1";
end if;
end if;
end if;
term_cnt <= not q_out(0) and q_out(1) and q_out(2) after 1 ns;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntarl10 is
port(ar, load, clk, clk_en : in std_logic;
d_in: in std_logic_vector(3 downto 0);
term_cnt : inout std_logic);
end;
architecture behavior of cntarl10 is
begin
process (ar, load, clk, clk_en)
variable q_out: std_logic_vector(3 downto 0);
begin
if ar = '1' then
q_out := "0000";
elsif (clk = '1' and clk'event) then
if (clk_en = '1') then
if load = '1' then
q_out := d_in;
elsif term_cnt = '1' then
q_out := "0000";
else
q_out := q_out + "1";
end if;
end if;
end if;
term_cnt <= q_out(0) and not q_out(1) and not q_out(2) and q_out(3) after 1 ns;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity accl4 is
port(d_in : in std_logic_vector(3 downto 0);
c_in : in std_logic;
clk, ce, load, ar : in std_logic;
c_out : out std_logic;
q_out : out std_logic_vector(3 downto 0));
end;
architecture behavior of accl4 is
signal sReg: std_logic_vector(3 downto 0);
signal sCout: std_logic;
signal sAdd : std_logic_vector(3 downto 0);
begin
add4:
process(c_in, d_in, sReg)
variable vCarry: std_logic;
variable vTemp : std_logic;
begin
vCarry := c_in;
for i in 0 to sAdd'length-1 loop
vTemp := d_in(i) xor sReg(i);
sAdd(i) <= vTemp xor vCarry;
vCarry := (d_in(i) and sReg(i)) or (vCarry and vTemp);
end loop;
sCout <= vCarry;
end process;
reg4:
process(ar, clk, ce, load, sAdd, d_in, sReg)
begin
if ar = '1' then
sReg <= "0000" after 2 ns;
c_out <= '0' after 2 ns;
elsif (clk = '1' and clk'event) then
if ce = '1' then
if load = '1' then
sReg <= d_in after 2 ns;
else
sReg <= sAdd;
c_out <= sCout;
end if;
end if;
end if;
q_out <= sReg;
end process;
end;
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