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module ABexp(A,B,Y,on_A,on_B);
input A;
inout B;
output Y;
input on_A,on_B;
reg Y;
wire ben;
assign ben=on_A & on_B;
assign B=ben?A:1'bz;
always
case ({on_A,on_B})
{1'b1,1'b0}:Y=A;
{1'b0,1'b1}:Y=B;
{1'b1,1'b1}:Y=A;
default:Y=1'bz;
endcase
endmodule
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