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Все прошло нормально. Ошибок не выдал.
Вот результаты для переменной и сигнала.
==VARIABLE ==
Synplify:
Mapping to part: xc9536xlvq64-5
Simple gate primitives:
FDCE 5 uses
AND2 20 uses
OR2 9 uses
XOR2 3 uses
I/O primitives:
IBUF 6 uses
OBUF 5 uses
BUFG 1 use
Xilinx (fitting report):
Resource Summary
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
5 /36 ( 13%) 20 /180 ( 11%) 5 /36 ( 13%) 12 /36 ( 33%) 17 /108 ( 15%)
== SIGNAL ==
Synplify:
Mapping to part: xc9536xlvq64-5
Simple gate primitives:
FDCE 5 uses
AND2 16 uses
OR2 6 uses
XOR2 3 uses
I/O primitives:
IBUF 6 uses
OBUF 5 uses
BUFG 1 use
Xilinx (fitting report):
Resource Summary
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
5 /36 ( 13%) 16 /180 ( 8%) 5 /36 ( 13%) 12 /36 ( 33%) 17 /108 ( 15%)
Вообщем, с сигналом немного лучше.
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