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На 4.2 синтезируется без ошибок, скорее всего дело в настройках
(«Телесистемы»: Конференция «Языки описания аппаратуры (VHDL и др.))

миниатюрный аудио-видеорекордер mAVR

Отправлено bryk 13 ноября 2002 г. 11:20
В ответ на: синтез компонента отправлено Serg_amon 12 ноября 2002 г. 12:00

Release 4.2i - xst E.35
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.55 s | Elapsed : 0.00 / 0.00 s

--> WARNING:Xst:15 - skipping parameter : dumpdir
CPU : 0.00 / 0.55 s | Elapsed : 0.00 / 0.00 s

--> Parameter overwrite set to YES
CPU : 0.00 / 0.55 s | Elapsed : 0.00 / 0.00 s

--> =========================================================================
---- Source Parameters
Input File Name : ppmain.prj
Input Format : Verilog

---- Target Parameters
Output File Name : ppmain.ngc
Output Format : NGC
Target Technology : 9500

---- Source Options
Top Module Name : ppmain
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Mux Extraction : YES
XOR Collapsing : YES

---- Target Options
Add IO Buffers : YES
Macro Generator : Macro+
MACRO Preserve : YES
XOR Preserve : YES
FF Optimization : YES
Flatten Hierarchy : NO

---- General Options
Optimization Criterion : Speed
Optimization Effort : 1

=========================================================================


Compiling source file : ppmain.prj
Compiling included source file 'ppmain.vf'
Module compiled.
Module compiled.
Continuing compilation of source file 'ppmain.prj'
Compiling included source file 'C:/Xilinx/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'ppmain.prj'
Compiling included source file 'C:/Xilinx/verilog/src/iSE/abel/aim.v'
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
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Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
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Module compiled.
Module compiled.
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Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Module compiled.
Continuing compilation of source file 'ppmain.prj'
No errors in compilation
Analysis of file succeeded.


Starting Verilog synthesis.

Analyzing module .
Module is correct for synthesis.

Analyzing module .
Generating a Black Box for module .

Analyzing top module .
Module is correct for synthesis.
Set property "load_kiss = AIM_ppmain_states.kis" for unit .
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.

Synthesizing Unit .
Related source file is C:/Xilinx/verilog/src/iSE/abel/aim.v.
Found 1-bit register for signal .
WARNING:Xst:647 - Input is never used.
WARNING:Xst:647 - Input is never used.
Summary:
inferred 1 D-type flip-flop(s).
Unit synthesized.

Loading KISS file AIM_ppmain_states.kis.
FSM description loaded for component .


Synthesizing Unit .
Related source file is ppmain.vf.
WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:646 - Signal is assigned but never used.
Summary:
inferred 1 Finite State Machine(s).
Unit synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers : 1
1-bit register : 1

=========================================================================

Selecting encoding for AIM_ppmain_states ...
Skipping local minimization (already done)
Skipping local minimization (already done)
Skipping local minimization (already done)
Skipping local minimization (already done)
Skipping local minimization (already done)
Skipping local minimization (already done)
Encoding for AIM_ppmain_states is Gray, flip-flop = T

Starting low level synthesis...

Optimizing unit ...

Optimizing unit ...

Merging netlists...

=========================================================================
Final Results
Output File Name : ppmain
Output Format : NGC
Optimization Criterion : Speed
Target Technology : 9500
Keep Hierarchy : yes
Macro Preserve : YES
Macro Generation : Macro+
XOR Preserve : YES

Design Statistics
# Edif Instances : 51
# I/Os : 15

=========================================================================
CPU : 1.15 / 1.70 s | Elapsed : 1.00 / 1.00 s

-->

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