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Release 4.2i - xst E.35
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
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--> WARNING:Xst:15 - skipping parameter : dumpdir
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--> Parameter overwrite set to YES
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--> =========================================================================
---- Source Parameters
Input File Name : ppmain.prj
Input Format : Verilog
---- Target Parameters
Output File Name : ppmain.ngc
Output Format : NGC
Target Technology : 9500
---- Source Options
Top Module Name : ppmain
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Mux Extraction : YES
XOR Collapsing : YES
---- Target Options
Add IO Buffers : YES
Macro Generator : Macro+
MACRO Preserve : YES
XOR Preserve : YES
FF Optimization : YES
Flatten Hierarchy : NO
---- General Options
Optimization Criterion : Speed
Optimization Effort : 1
=========================================================================
Synthesizing Unit Loading KISS file AIM_ppmain_states.kis. ========================================================================= Macro Statistics ========================================================================= Selecting encoding for AIM_ppmain_states ... Starting low level synthesis... Optimizing unit Optimizing unit Merging netlists... ========================================================================= Design Statistics =========================================================================
E-mail:
info@telesys.ru
Compiling source file : ppmain.prj
Compiling included source file 'ppmain.vf'
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Continuing compilation of source file 'ppmain.prj'
Compiling included source file 'C:/Xilinx/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'ppmain.prj'
Compiling included source file 'C:/Xilinx/verilog/src/iSE/abel/aim.v'
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Continuing compilation of source file 'ppmain.prj'
No errors in compilation
Analysis of file
Starting Verilog synthesis.
Analyzing module
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Analyzing module
Generating a Black Box for module
Analyzing top module
Module
Set property "load_kiss = AIM_ppmain_states.kis" for unit
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.
Related source file is C:/Xilinx/verilog/src/iSE/abel/aim.v.
Found 1-bit register for signal .
WARNING:Xst:647 - Input
WARNING:Xst:647 - Input
Summary:
inferred 1 D-type flip-flop(s).
Unit
FSM description loaded for component
Synthesizing Unit
Related source file is ppmain.vf.
WARNING:Xst:646 - Signal
WARNING:Xst:646 - Signal
WARNING:Xst:646 - Signal
WARNING:Xst:646 - Signal
WARNING:Xst:646 - Signal
WARNING:Xst:646 - Signal
WARNING:Xst:646 - Signal
Summary:
inferred 1 Finite State Machine(s).
Unit
HDL Synthesis Report
# Registers : 1
1-bit register : 1
Skipping local minimization (already done)
Skipping local minimization (already done)
Skipping local minimization (already done)
Skipping local minimization (already done)
Skipping local minimization (already done)
Skipping local minimization (already done)
Encoding for AIM_ppmain_states is Gray, flip-flop = T
Final Results
Output File Name : ppmain
Output Format : NGC
Optimization Criterion : Speed
Target Technology : 9500
Keep Hierarchy : yes
Macro Preserve : YES
Macro Generation : Macro+
XOR Preserve : YES
# Edif Instances : 51
# I/Os : 15
CPU : 1.15 / 1.70 s | Elapsed : 1.00 / 1.00 s
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