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module ass1(a,b,c,d);
input[3:0] a, b;
input c;
output[3:0] d;
reg [3:0] d;
always@(a or c) if (c) d<=a+b;
//always @(a or b or c) if (c) d <= a + b;
endmodule
module ass2(a,b,c,d);
input[3:0] a, b;
input c;
output[3:0] d;
reg [3:0] d;
//always@(a or c) if (c) d<=a+b;
always @(a or b or c) if (c) d <= a + b;
endmodule
module test;
reg a,b,c;
wire d1,d2;
ass1 m1(a,b,c,d1);
ass2 m2(a,b,c,d2);
initial
begin
$monitor($time,a,b,c,d1,d2);
a=0;b=0;c=0;
#5 c=1;
#10 b=1;
#10 b=0;
#10 b=1;
#10 b=0;
end
endmodule
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