Отправлено vitA 06 апреля 2001 г. 00:47 В ответ на: В ACEXе есть ячейки озу - как их описать и использовать на языке VHDL? Такое вообще возможно? отправлено Mike 04 апреля 2001 г. 18:49

U Leonardo est' primer (nazivaetsia RAM.vhd), gde pokazano kak na VHDL ispol'zovat' vsroennie iacheiki RAM v chipah ALTERA:
--
-- The following information has been generated by Exemplar Logic
-- and may be freely distributed and modified.
--
-- Design name : ram
--
-- Purpose : This design is a generic ram. Both the address and data
-- have programmable widths. This ram can be used in place
-- of technology specific rams.
--
----------------------------------------------------------------------------
Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;

entity ram is
generic (data_width : natural := 8 ;
address_width : natural := 8);
port (
data_in : in UNSIGNED(data_width - 1 downto 0) ;
address : in UNSIGNED(address_width - 1 downto 0) ;
we : in std_logic ;
data_out : out UNSIGNED(data_width - 1 downto 0)
);
end ram ;

architecture rtl of ram is
type mem_type is array (2**address_width downto 0) of
UNSIGNED(data_width - 1 downto 0) ;
signal mem : mem_type ;
begin
I0 : process (we,address,mem,data_in)
begin
if (we = '1') then
mem(conv_integer(address)) <= data_in ;
end if ;
data_out <= mem(conv_integer(address)) ;
end process ;
end RTL ;