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/****************************************************************************
** - iom162.h -
**
** This file declares the internal register addresses for ATmega162.
**
** Used with iccAVR and aAVR.
**
** Copyright IAR Systems 2002. All rights reserved.
**
** $Name: V3_10B V3_10A_EV V3_10A_PRO V3_10A $
**
***************************************************************************/
#include "iomacro.h"
#if TID_GUARD(3)
#error This file should only be compiled with iccavr or aavr whith processor option -v3
#endif /* TID_GUARD(3) */
#ifdef __HAS_RAMPZ__
#error This file should not have RAMPZ enabled, use --cpu or --64k_flash
#endif /* __HAS_RAMPZ__ */
/* Include the SFR part if this file has not been included before,
* OR this file is included by the assembler (SFRs must be defined in
* each assembler module). */
#if !defined(__IOM162_H) || defined(__IAR_SYSTEMS_ASM__)
#pragma language=extended
/*==========================*/
/* Predefined SFR Addresses */
/*==========================*/
/****************************************************************************
* An example showing the SFR_B() macro call,
* the expanded result and usage of this result:
*
* SFR_B(AVR, 0x1F) Expands to:
* __io union {
* unsigned char AVR; // The sfrb as 1 byte
* struct { // The sfrb as 8 bits
* unsigned char AVR_Bit0:1,
* AVR_Bit1:1,
* AVR_Bit2:1,
* AVR_Bit3:1,
* AVR_Bit4:1,
* AVR_Bit5:1,
* AVR_Bit6:1,
* AVR_Bit7:1;
* };
* } @ 0x1F;
* Examples of how to use the expanded result:
* AVR |= (1<<5);
* or like this:
* AVR_Bit5 = 1;
***************************************************************************/
SFR_B(UBRR1L, 0x00) /* USART1 Baud Rate Register Low */
SFR_B(UCSR1B, 0x01) /* USART1 Control and Status Register B */
SFR_B(UCSR1A, 0x02) /* USART1 Control and Status Register A */
SFR_B(UDR1, 0x03) /* USART1 I/O Data Register */
SFR_B2(OCDR, OSCCAL, 0x04)/* On-chip Debug Register and Oscillator Calibration Register */
SFR_B(PINE, 0x05) /* Input Pins, Port E */
SFR_B(DDRE, 0x06) /* Data Direction Register, Port E */
SFR_B(PORTE, 0x07) /* Data Register, Port E */
SFR_B(ACSR, 0x08) /* Analog Comparator Control and Status Register */
SFR_B(UBRR0L, 0x09) /* USART0 Baud Rate Register Low*/
SFR_B(UCSR0B, 0x0A) /* USART0 Control and Status Register B */
SFR_B(UCSR0A, 0x0B) /* USART0 Control and Status Register A */
SFR_B(UDR0, 0x0C) /* USART0 I/O Data Register */
SFR_B(SPCR, 0x0D) /* SPI Control Register */
SFR_B(SPSR, 0x0E) /* SPI Status Register */
SFR_B(SPDR, 0x0F) /* SPI I/O Data Register */
SFR_B(PIND, 0x10) /* Input Pins, Port D */
SFR_B(DDRD, 0x11) /* Data Direction Register, Port D */
SFR_B(PORTD, 0x12) /* Data Register, Port D */
SFR_B(PINC, 0x13) /* Input Pins, Port C */
SFR_B(DDRC, 0x14) /* Data Direction Register, Port C */
SFR_B(PORTC, 0x15) /* Data Register, Port C */
SFR_B(PINB, 0x16) /* Input Pins, Port B */
SFR_B(DDRB, 0x17) /* Data Direction Register, Port B */
SFR_B(PORTB, 0x18) /* Data Register, Port B */
SFR_B(PINA, 0x19) /* Input Pins, Port A */
SFR_B(DDRA, 0x1A) /* Data Direction Register, Port A */
SFR_B(PORTA, 0x1B) /* Data Register, Port A */
SFR_B(EECR, 0x1C) /* EEPROM Control Register */
SFR_B(EEDR, 0x1D) /* EEPROM Data Register */
SFR_W(EEAR, 0x1E) /* EEPROM Address Register */
SFR_B2(UBRR0H, UCSR0C, 0x20)/* USART0 Baud Rate Register High and Control and Status Register C */
SFR_B(WDTCR, 0x21) /* Watchdog Timer Control Register */
SFR_B(OCR2, 0x22) /* Timer/Counter 2 Output Compare Register */
SFR_B(TCNT2, 0x23) /* Timer/Counter 2 */
SFR_W(ICR1, 0x24) /* Timer/Counter 1 Input Capture Register */
SFR_B(ASSR, 0x26) /* Asynchronous mode Status Register */
SFR_B(TCCR2, 0x27) /* Timer/Counter 2 Control Register */
SFR_W(OCR1B, 0x28) /* Timer/Counter 1 Output Compare Register B */
SFR_W(OCR1A, 0x2A) /* Timer/Counter 1 Output Compare Register A */
SFR_W(TCNT1, 0x2C) /* Timer/Counter 1 Register */
SFR_B(TCCR1B, 0x2E) /* Timer/Counter 1 Control Register B */
SFR_B(TCCR1A, 0x2F) /* Timer/Counter 1 Control Register A */
SFR_B(SFIOR, 0x30) /* Special Function I/O Register */
SFR_B(OCR0, 0x31) /* Timer/Counter 0 Output Compare Register */
SFR_B(TCNT0, 0x32) /* Timer/Counter 0 */
SFR_B(TCCR0, 0x33) /* Timer/Counter 0 Control Register */
SFR_B(MCUCSR, 0x34) /* MCU general Control and Status Register */
SFR_B(MCUCR, 0x35) /* MCU general Control Register */
SFR_B(EMCUCR, 0x36) /* Extended MCU general Control Register */
SFR_B(SPMCR, 0x37) /* Store Program Memory Control Register */
SFR_B(TIFR, 0x38) /* Timer/Counter Interrupt Flag Register */
SFR_B(TIMSK, 0x39) /* Timer/Counter Interrupt Mask Register */
SFR_B(GIFR, 0x3A) /* General Interrupt Flag Register */
SFR_B(GICR, 0x3B) /* General Interrupt Control Register */
SFR_B2(UBRR1H, UCSR1C, 0x3C)/* USART1 Baud Rate Register High and USART1 Control and Status Register C */
SFR_W(SP, 0x3D) /* Stack Pointer */
SFR_B(SREG, 0x3F) /* Status Register */
/* Extended I/O space */
SFR_B_EXT(CLKPR, 0x61) /* System Clock Prescaler */
SFR_B_EXT(PCMSK0, 0x6B) /* Pin Change Mask Register 0 */
SFR_B_EXT(PCMSK1, 0x6C) /* Pin Change Mask Register 1 */
SFR_B_EXT(ETIFR, 0x7C) /* Extended Timer/Counter Interrupt Flag Register */
SFR_B_EXT(ETIMSK, 0x7D) /* Extended Timer/Counter Interrupt Mask Register */
SFR_B_EXT(ICR3L, 0x80) /* Timer/Counter 3 Input Capture Register Low */
SFR_B_EXT(ICR3H, 0x81) /* Timer/Counter 3 Input Capture Register High */
SFR_B_EXT(OCR3BL, 0x84) /* Timer/Counter 3 Output Compare Register B Low */
SFR_B_EXT(OCR3BH, 0x85) /* Timer/Counter 3 Output Compare Register B High */
SFR_B_EXT(OCR3AL, 0x86) /* Timer/Counter 3 Output Compare Register A Low */
SFR_B_EXT(OCR3AH, 0x87) /* Timer/Counter 3 Output Compare Register A High */
SFR_B_EXT(TCNT3L, 0x88) /* Timer/Counter 3 Register Low */
SFR_B_EXT(TCNT3H, 0x89) /* Timer/Counter 3 Register High */
SFR_B_EXT(TCCR3B, 0x8A) /* Timer/Counter 3 Control Register B */
SFR_B_EXT(TCCR3A, 0x8B) /* Timer/Counter 3 Control Register A */
#ifndef __IOM162_H
#define __IOM162_H
/* SFRs are local in assembler modules (so this file may need to be */
/* included in more than one module in the same source file), */
/* but #defines must only be made once per source file. */
/*==============================*/
/* Interrupt Vector Definitions */
/*==============================*/
/* NB! vectors are specified as byte addresses */
#ifndef __M161C__ //Define __M161C__ when you want to run in Mega161 compability mode.
#define RESET_vect (0x00)
#define INT0_vect (0x04)
#define INT1_vect (0x08)
#define INT2_vect (0x0C)
#define PCINT0_vect (0x10)
#define PCINT1_vect (0x14)
#define TIMER3_CAPT_vect (0x18)
#define TIMER3_COMPA_vect (0x1C)
#define TIMER3_COMPB_vect (0x20)
#define TIMER3_OVF_vect (0x24)
#define TIMER2_COMP_vect (0x28)
#define TIMER2_OVF_vect (0x2C)
#define TIMER1_CAPT_vect (0x30)
#define TIMER1_COMPA_vect (0x34)
#define TIMER1_COMPB_vect (0x38)
#define TIMER1_OVF_vect (0x3C)
#define TIMER0_COMP_vect (0x40)
#define TIMER0_OVF_vect (0x44)
#define SPI_STC_vect (0x48)
#define USART0_RXC_vect (0x4C)
#define USART1_RXC_vect (0x50)
#define USART0_UDRE_vect (0x54)
#define USART1_UDRE_vect (0x58)
#define USART0_TXC_vect (0x5C)
#define USART1_TXC_vect (0x60)
#define EE_RDY_vect (0x64)
#define ANA_COMP_vect (0x68)
#define SPM_RDY_vect (0x6C)
#else
#define RESET_vect (0x00)
#define INT0_vect (0x04)
#define INT1_vect (0x08)
#define INT2_vect (0x0C)
#define TIMER2_COMP_vect (0x10)
#define TIMER2_OVF_vect (0x14)
#define TIMER1_CAPT_vect (0x18)
#define TIMER1_COMPA_vect (0x1C)
#define TIMER1_COMPB_vect (0x20)
#define TIMER1_OVF_vect (0x24)
#define TIMER0_COMP_vect (0x28)
#define TIMER0_OVF_vect (0x2C)
#define SPI_STC_vect (0x30)
#define USART0_RX_vect (0x34)
#define USART1_RX_vect (0x38)
#define USART0_UDRE_vect (0x3C)
#define USART1_UDRE_vect (0x40)
#define USART0_TX_vect (0x44)
#define USART1_TX_vect (0x48)
#define EE_RDY_vect (0x4C)
#define ANA_COMP_vect (0x50)
#define SPM_RDY_vect (0x54)
#endif
#ifdef __IAR_SYSTEMS_ASM__
#ifndef ENABLE_BIT_DEFINITIONS
#define ENABLE_BIT_DEFINITIONS
#endif /* ENABLE_BIT_DEFINITIONS */
#endif /* __IAR_SYSTEMS_ASM__ */
#ifdef ENABLE_BIT_DEFINITIONS
/* Bit definitions for use with the IAR Assembler
The Register Bit names are represented by their bit number (0-7).
*/
/* Timer/Counter 3 Control Register A */
#define COM3A1 7
#define COM3A0 6
#define COM3B1 5
#define COM3B0 4
#define FOC3A 3
#define FOC3B 2
#define WGM31 1
#define WGM30 0
/* Timer/Counter 3 Control Register B */
#define ICNC3 7
#define ICES3 6
#define WGM33 4
#define WGM32 3
#define CS32 2
#define CS31 1
#define CS30 0
/* Extended Timer/Counter Interrupt Mask Register */
#define TICIE3 5
#define OCIE3A 4
#define OCIE3B 3
#define TOIE3 2
/* Extended Timer/Counter Interrupt Flag Register */
#define ICF3 5
#define OCF3A 4
#define OCF3B 3
#define TOV3 2
/* Pin Change Mask Register 1 */
#define PCINT15 7
#define PCINT14 6
#define PCINT13 5
#define PCINT12 4
#define PCINT11 3
#define PCINT10 2
#define PCINT9 1
#define PCINT8 0
/* Pin Change Mask Register 0 */
#define PCINT7 7
#define PCINT6 6
#define PCINT5 5
#define PCINT4 4
#define PCINT3 3
#define PCINT2 2
#define PCINT1 1
#define PCINT0 0
/* Clock Prescale Register */
#define CLKPCE 7
#define CLKPS3 3
#define CLKPS2 2
#define CLKPS1 1
#define CLKPS0 0
/* USART UBRRH1 and UCSRC1 */
#define URSEL1 7
#define UMSEL1 6
#define UPM11 5
#define UPM10 4
#define USBS1 3
#define UCSZ11 2
#define UCSZ10 1
#define UCPOL1 0
/* General Interrupt Control register */
#define INT1 7
#define INT0 6
#define INT2 5
#define PCIE1 4
#define PCIE0 3
#define IVSEL 1
#define IVCE 0
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
#define INTF2 5
#define PCIF1 4
#define PCIF0 3
/* Timer/Counter Interrupt MaSK register */
#define TOIE1 7
#define OCIE1A 6
#define OCIE1B 5
#define OCIE2 4
#define TICIE1 3
#define TOIE2 2
#define TOIE0 1
#define OCIE0 0
/* Timer/Counter Interrupt Flag register */
#define TOV1 7
#define OCF1A 6
#define OCF1B 5
#define OCF2 4
#define ICF1 3
#define TOV2 2
#define TOV0 1
#define OCF0 0
/* SPM Control Register */
#define SPMIE 7
#define RWWSB 6
#define RWWSRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* Extended MCU general Control Register */
#define SM0 7
#define SRL2 6
#define SRL1 5
#define SRL0 4
#define SRW01 3
#define SRW00 2
#define SRW11 1
#define ISC2 0
/* MCU general Control Register */
#define SRE 7
#define SRW10 6
#define SE 5
#define SM1 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* MCU general Control and Status Register */
#define JTD 7
#define SM2 5
#define JTRF 4
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* Timer/Counter 0 Control Register */
#define FOC0 7
#define WGM00 6
#define COM01 5
#define COM00 4
#define WGM01 3
#define CS02 2
#define CS01 1
#define CS00 0
/* Special Function I/O Register */
#define TSM 7
#define XMBK 6
#define XMM2 5
#define XMM1 4
#define XMM0 3
#define PUD 2
#define PSR2 1
#define PSR310 0
/* Timer/Counter 0 Control Register A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define FOC1A 3
#define FOC1B 2
#define WGM11 1
#define WGM10 0
/* Timer/Counter 0 Control Register B */
#define ICNC1 7
#define ICES1 6
#define WGM13 4
#define WGM12 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Timer/Counter2 Control Register */
#define FOC2 7
#define WGM20 6
#define COM21 5
#define COM20 4
#define WGM21 3
#define CS22 2
#define CS21 1
#define CS20 0
/* Asyncronous Status Register */
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* Watchdog Timer Control Register */
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* USART UBRRH0 and UCSRC0 */
#define URSEL0 7
#define UMSEL0 6
#define UPM01 5
#define UPM00 4
#define USBS0 3
#define UCSZ01 2
#define UCSZ00 1
#define UCPOL0 0
/* EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* Data Register, Port A */
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
/* Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* Data Register, Port B */
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Data Register, Port C */
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
/* Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Data Register, Port D */
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* SPI Status Register */
#define SPIF 7
#define WCOL 6
#define SPI2X 0
/* SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* USART0 Control and Status Register A */
#define RXC0 7
#define TXC0 6
#define UDRE0 5
#define FE0 4
#define DOR0 3
#define UPE0 2
#define U2X0 1
#define MPCM0 0
/* USART0 Control and Status Register B */
#define RXCIE0 7
#define TXCIE0 6
#define UDRIE0 5
#define RXEN0 4
#define TXEN0 3
#define UCSZ02 2
#define RXB80 1
#define TXB80 0
/* Analog Comparator Control And Status Register */
#define ACD 7
#define ACBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* Data Register, Port E */
#define PE2 2
#define PE1 1
#define PE0 0
/* Data Register, Port E */
#define PORTE2 2
#define PORTE1 1
#define PORTE0 0
/* Data Direction Register, Port E */
#define DDE2 2
#define DDE1 1
#define DDE0 0
/* Input Pins, Port E */
#define PINE2 2
#define PINE1 1
#define PINE0 0
/* USART1 Control and Status Register A */
#define RXC1 7
#define TXC1 6
#define UDRE1 5
#define FE1 4
#define DOR1 3
#define UPE1 2
#define U2X1 1
#define MPCM1 0
/* USART1 Control and Status Register B */
#define RXCIE1 7
#define TXCIE1 6
#define UDRIE1 5
#define RXEN1 4
#define TXEN1 3
#define UCSZ12 2
#define RXB81 1
#define TXB81 0
/* Pointer definition */
#define XL r26
#define XH r27
#define YL r28
#define YH r29
#define ZL r30
#define ZH r31
/* Contants */
#define RAMEND 0x04FF /*Last On-Chip SRAM location*/
#define XRAMEND 0xFFFF
#define E2END 0x01FF
#define FLASHEND 0x3FFF
#endif /* ENABLE_BIT_DEFINITIONS */
#endif /* __IOM162_H (define part) */
#endif /* __IOM162_H (SFR part) */
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