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SFRPAGE_SAVEP = SFRPAGE; // Save Current SFR page
SFRPAGE = CONFIG_PAGE; // set SFR page
OSCICN = 0x83; // set internal oscillator to run
// at its maximum frequency
CLKSEL = 0x00; // Select the internal osc. as
// the SYSCLK source
SFRPAGE = CONFIG_PAGE;
PLL0CN = 0x00; // Set internal osc. as PLL source
SFRPAGE = LEGACY_PAGE;
FLSCL = 0x30; // Set FLASH read time for 100MHz clk
// or less
SFRPAGE = CONFIG_PAGE;
PLL0CN |= 0x01; // Enable Power to PLL
PLL0DIV = 0x01; // Set Pre-divide value to N (N = 1)
PLL0FLT = 0x01;
PLL0MUL = 0x04; // Multiply SYSCLK by M (M = 4) 100MHz
Delay(10); // Wait at least 5us
PLL0CN |= 0x02; // Enable the PLL
while(!(PLL0CN & 0x10)); // Wait until PLL frequency is locked
CLKSEL = 0x02; // Select PLL as SYSCLK source
SFRPAGE = SFRPAGE_SAVEP;
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