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module sqrt(clk,ld,y,x,flag);
parameter width=64, sqwidth=width/2, logsqwidth=5;
wire [sqwidth-2-1:0] zeros=0;
input ld,clk;
input [width-1:0] y;
output [sqwidth-1:0] x;
output flag;
reg [sqwidth-1:0] x;
reg flag;
reg [width-1:0] z;
wire [width-1:0] delta;
reg [width-1-2:0] a;
reg [logsqwidth-1:0] i;
//always @(negedge clk) delta={z[width-1-2:0],a[width-1-2:width-1-3]}-{zeros,x[sqwidth-1:0],2'b01};
assign delta={z[width-1-2:0],a[width-1-2:width-1-3]}-{zeros,x[sqwidth-1:0],2'b01};
always @(posedge clk)
if (ld)
begin
flag=0;
i=0;
a=y[width-1-2:0];
if (y[width-1:width-2]==0)
x=0;
else
x=1;
case (y[width-1:width-2])
0,1: z=0;
2: z=1;
3: z=2;
endcase
end
else
begin
if (i!=sqwidth-1)
begin
i=i+1;
// a=a<<2;
if (delta[width-1])
begin
x={x[sqwidth-1-1:0],1'b0};
z={z[width-1-2:0],a[width-1-2:width-1-3]};
end
else
begin
x={x[sqwidth-1-1:0],1'b1};
z=delta;
end
a=a<<2;
end
else flag=1;
end
endmodule
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