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/* header file for the MICROCHIP PIC microcontrollers
* PIC16F630
* PIC16F676
*/#ifndef __PIC16630_H
#define __PIC16630_H// Special function register definitions
static volatile unsigned char TMR0 @ 0x01;
static volatile unsigned char PCL @ 0x02;
static volatile unsigned char STATUS @ 0x03;
static unsigned char FSR @ 0x04;
static volatile unsigned char PORTA @ 0x05;
static volatile unsigned char PORTC @ 0x07;
static volatile unsigned char PCLATH @ 0x0A;
static volatile unsigned char INTCON @ 0x0B;
static volatile unsigned char PIR1 @ 0x0C;
static volatile unsigned char TMR1L @ 0x0E;
static volatile unsigned char TMR1H @ 0x0F;
static unsigned char T1CON @ 0x10;
static volatile unsigned char CMCON @ 0x19;
#if defined(_16F676)
static volatile unsigned char ADRESH @ 0x1E;
static volatile unsigned char ADCON0 @ 0x1F;
#endif
static bank1 unsigned char OPTION @ 0x81;
static volatile bank1 unsigned char TRISA @ 0x85;
static volatile bank1 unsigned char TRISC @ 0x87;
static bank1 unsigned char PIE1 @ 0x8C;
static volatile bank1 unsigned char PCON @ 0x8E;
static bank1 unsigned char OSCCAL @ 0x90;
#if defined(_16F676)
static bank1 unsigned char ANSEL @ 0x91;
#endif
static bank1 unsigned char WPUA @ 0x95;
static bank1 unsigned char IOCA @ 0x96;
static bank1 unsigned char VRCON @ 0x99;
static volatile bank1 unsigned char EEDAT @ 0x9A;
// alternate definition
static volatile bank1 unsigned char EEDATA @ 0x9A;
static bank1 unsigned char EEADR @ 0x9B;
static volatile bank1 unsigned char EECON1 @ 0x9C;
static volatile bank1 unsigned char EECON2 @ 0x9D;
#if defined(_16F676)
static volatile bank1 unsigned char ADRESL @ 0x9E;
static bank1 unsigned char ADCON1 @ 0x9F;
#endif
/* Definitions for STATUS register */
static volatile bit CARRY @((unsigned)&STATUS*8)+0;
static volatile bit DC @((unsigned)&STATUS*8)+1;
static volatile bit ZERO @((unsigned)&STATUS*8)+2;
static volatile bit PD @((unsigned)&STATUS*8)+3;
static volatile bit TO @((unsigned)&STATUS*8)+4;
static bit RP0 @((unsigned)&STATUS*8)+5;/* Definitions for PORTA register */
static volatile bit RA0 @((unsigned)&PORTA*8)+0;
static volatile bit RA1 @((unsigned)&PORTA*8)+1;
static volatile bit RA2 @((unsigned)&PORTA*8)+2;
static volatile bit RA3 @((unsigned)&PORTA*8)+3;
static volatile bit RA4 @((unsigned)&PORTA*8)+4;
static volatile bit RA5 @((unsigned)&PORTA*8)+5;/* Definitions for PORTC register */
static volatile bit RC0 @((unsigned)&PORTC*8)+0;
static volatile bit RC1 @((unsigned)&PORTC*8)+1;
static volatile bit RC2 @((unsigned)&PORTC*8)+2;
static volatile bit RC3 @((unsigned)&PORTC*8)+3;
static volatile bit RC4 @((unsigned)&PORTC*8)+4;
static volatile bit RC5 @((unsigned)&PORTC*8)+5;/* Definitions for INTCON register */
static volatile bit RAIF @((unsigned)&INTCON*8)+0;
static volatile bit INTF @((unsigned)&INTCON*8)+1;
static volatile bit T0IF @((unsigned)&INTCON*8)+2;
static bit RAIE @((unsigned)&INTCON*8)+3;
static bit INTE @((unsigned)&INTCON*8)+4;
static bit T0IE @((unsigned)&INTCON*8)+5;
static bit PEIE @((unsigned)&INTCON*8)+6;
static bit GIE @((unsigned)&INTCON*8)+7;/* Definitions for PIR1 register */
static volatile bit TMR1IF @((unsigned)&PIR1*8)+0;
static volatile bit CMIF @((unsigned)&PIR1*8)+3;
#if defined(_16F676)
static volatile bit ADIF @((unsigned)&PIR1*8)+6;
#endif
static volatile bit EEIF @((unsigned)&PIR1*8)+7;/* Definitions for T1CON register */
static bit TMR1ON @((unsigned)&T1CON*8)+0;
static bit TMR1CS @((unsigned)&T1CON*8)+1;
static bit T1SYNC @((unsigned)&T1CON*8)+2;
static bit T1OSCEN @((unsigned)&T1CON*8)+3;
static bit T1CKPS0 @((unsigned)&T1CON*8)+4;
static bit T1CKPS1 @((unsigned)&T1CON*8)+5;
static bit T1GE @((unsigned)&T1CON*8)+6;
// alternate definition
static bit TMR1GE @((unsigned)&T1CON*8)+6;/* Definitions for CMCON register */
static bit CM0 @((unsigned)&CMCON*8)+0;
static bit CM1 @((unsigned)&CMCON*8)+1;
static bit CM2 @((unsigned)&CMCON*8)+2;
static bit CIS @((unsigned)&CMCON*8)+3;
static bit CINV @((unsigned)&CMCON*8)+4;
static volatile bit COUT @((unsigned)&CMCON*8)+6;#if defined(_16F676)
/* Definitions for ADCON0 register */
static bit ADON @((unsigned)&ADCON0*8)+0;
static volatile bit GODONE @((unsigned)&ADCON0*8)+1;
static bit CHS0 @((unsigned)&ADCON0*8)+2;
static bit CHS1 @((unsigned)&ADCON0*8)+3;
static bit CHS2 @((unsigned)&ADCON0*8)+4;
static bit VCFG @((unsigned)&ADCON0*8)+6;
static bit ADFM @((unsigned)&ADCON0*8)+7;
#endif/* Definitions for OPTION register */
static bank1 bit PS0 @((unsigned)&OPTION*8)+0;
static bank1 bit PS1 @((unsigned)&OPTION*8)+1;
static bank1 bit PS2 @((unsigned)&OPTION*8)+2;
static bank1 bit PSA @((unsigned)&OPTION*8)+3;
static bank1 bit T0SE @((unsigned)&OPTION*8)+4;
static bank1 bit T0CS @((unsigned)&OPTION*8)+5;
static bank1 bit INTEDG @((unsigned)&OPTION*8)+6;
static bank1 bit RAPU @((unsigned)&OPTION*8)+7;/* Definitions for TRISA register */
static volatile bank1 bit TRISA0 @((unsigned)&TRISA*8)+0;
static volatile bank1 bit TRISA1 @((unsigned)&TRISA*8)+1;
static volatile bank1 bit TRISA2 @((unsigned)&TRISA*8)+2;
static volatile bank1 bit TRISA3 @((unsigned)&TRISA*8)+3;
static volatile bank1 bit TRISA4 @((unsigned)&TRISA*8)+4;
static volatile bank1 bit TRISA5 @((unsigned)&TRISA*8)+5;/* Definitions for TRISC register */
static volatile bank1 bit TRISC0 @((unsigned)&TRISC*8)+0;
static volatile bank1 bit TRISC1 @((unsigned)&TRISC*8)+1;
static volatile bank1 bit TRISC2 @((unsigned)&TRISC*8)+2;
static volatile bank1 bit TRISC3 @((unsigned)&TRISC*8)+3;
static volatile bank1 bit TRISC4 @((unsigned)&TRISC*8)+4;
static volatile bank1 bit TRISC5 @((unsigned)&TRISC*8)+5;/* Definitions for PIE1 register */
static bank1 bit TMR1IE @((unsigned)&PIE1*8)+0;
static bank1 bit CMIE @((unsigned)&PIE1*8)+3;
#if defined(_16F676)
static bank1 bit ADIE @((unsigned)&PIE1*8)+6;
#endif
static bank1 bit EEIE @((unsigned)&PIE1*8)+7;/* Definitions for PCON register */
static volatile bank1 bit BOR @((unsigned)&PCON*8)+0;
static volatile bank1 bit POR @((unsigned)&PCON*8)+1;/* Definitions for OSCCAL register */
static bank1 bit CAL0 @((unsigned)&OSCCAL*8)+2;
static bank1 bit CAL1 @((unsigned)&OSCCAL*8)+3;
static bank1 bit CAL2 @((unsigned)&OSCCAL*8)+4;
static bank1 bit CAL3 @((unsigned)&OSCCAL*8)+5;
static bank1 bit CAL4 @((unsigned)&OSCCAL*8)+6;
static bank1 bit CAL5 @((unsigned)&OSCCAL*8)+7;#if defined(_16F676)
/* Definitions for ANSEL register */
static bank1 bit ANS0 @((unsigned)&ANSEL*8)+0;
static bank1 bit ANS1 @((unsigned)&ANSEL*8)+1;
static bank1 bit ANS2 @((unsigned)&ANSEL*8)+2;
static bank1 bit ANS3 @((unsigned)&ANSEL*8)+3;
static bank1 bit ANS4 @((unsigned)&ANSEL*8)+4;
static bank1 bit ANS5 @((unsigned)&ANSEL*8)+5;
static bank1 bit ANS6 @((unsigned)&ANSEL*8)+6;
static bank1 bit ANS7 @((unsigned)&ANSEL*8)+7;
#endif/* Definitions for WPUA register */
static bank1 bit WPUA0 @((unsigned)&WPUA*8)+0;
static bank1 bit WPUA1 @((unsigned)&WPUA*8)+1;
static bank1 bit WPUA2 @((unsigned)&WPUA*8)+2;
static bank1 bit WPUA4 @((unsigned)&WPUA*8)+4;
static bank1 bit WPUA5 @((unsigned)&WPUA*8)+5;/* Definitions for IOCA register */
static bank1 bit IOCA0 @((unsigned)&IOCA*8)+0;
static bank1 bit IOCA1 @((unsigned)&IOCA*8)+1;
static bank1 bit IOCA2 @((unsigned)&IOCA*8)+2;
static bank1 bit IOCA3 @((unsigned)&IOCA*8)+3;
static bank1 bit IOCA4 @((unsigned)&IOCA*8)+4;
static bank1 bit IOCA5 @((unsigned)&IOCA*8)+5;/* Definitions for VRCON register */
static bank1 bit VR0 @((unsigned)&VRCON*8)+0;
static bank1 bit VR1 @((unsigned)&VRCON*8)+1;
static bank1 bit VR2 @((unsigned)&VRCON*8)+2;
static bank1 bit VR3 @((unsigned)&VRCON*8)+3;
static bank1 bit VRR @((unsigned)&VRCON*8)+5;
static bank1 bit VREN @((unsigned)&VRCON*8)+7;/* Definitions for EECON1 register */
static volatile bank1 bit RD @((unsigned)&EECON1*8)+0;
static volatile bank1 bit WR @((unsigned)&EECON1*8)+1;
static bank1 bit WREN @((unsigned)&EECON1*8)+2;
static volatile bank1 bit WRERR @((unsigned)&EECON1*8)+3;#if defined(_16F676)
/* Definitions for ADCON1 register */
static bank1 bit ADCS0 @((unsigned)&ADCON1*8)+4;
static bank1 bit ADCS1 @((unsigned)&ADCON1*8)+5;
static bank1 bit ADCS2 @((unsigned)&ADCON1*8)+6;
#endif#define _READ_OSCCAL_DATA() (*(unsigned char(*)())0x3FF)()
#define EEPROM_SIZE 128
/* macro versions of EEPROM write and read */
#define EEPROM_WRITE(addr, value) while(WR)continue;EEADR=(addr);EEDATA=(value); \
CARRY=0;if(GIE)CARRY=1;GIE=0; \
WREN=1;EECON2=0x55;EECON2=0xAA;WR=1;WREN=0; \
if(CARRY)GIE=1#define EEPROM_READ(addr) ((EEADR=(addr)),(RD=1),EEDATA)
/* library function versions */
extern void eeprom_write(unsigned char addr, unsigned char value);
extern unsigned char eeprom_read(unsigned char addr);#define CONFIG_ADDR 0x2007
// Configuration Mask Definitions
// bandgap calibration
#define BGHIGH 0x3FFF // highest bandgap voltage
#define BGLOW 0x0FFF // lowest bandgap volatage
// data code protection
#define CPD 0x3EFF // protect data memory
#define UNPROTECT 0x3FFF // do not protect memory
// code protection
#define CPROTECT 0x3F7F // protect program memory
// brown-out detect enable
#define BOREN 0x3FFF // brown-out reset enabled
#define BORDIS 0x3FBF // brown-out reset disabled
// RA3/MCLR pin function select
#define MCLREN 0x3FFF // MCLR pin function enabled
#define MCLRDIS 0x3FDF // MCLR pin function disabled
// power-up timer enable
#define PWRTEN 0x3FEF // power-up timer enabled
#define PWRTDIS 0x3FFF // power-up timer disabled
// watchdog timer enable
#define WDTEN 0x3FFF // watchdog timer enabled
#define WDTDIS 0x3FF7 // watchdog timer disabled
// oscillator selection
#define RCCLKO 0x3FFF // RC osc, RA4 pin is CLKOUT
#define RCIO 0x3FFE // RC osc, RA4 pin is IO
#define INTOSCCLKO 0x3FFD // INTOSC, RA4 pin is CLKOUT
#define INTOSCIO 0x3FFC // INTOSC, RA4 pin is IO
#define EC 0x3FFB // external clock
#define HS 0x3FFA // high speed XTAL/resonator
#define XT 0x3FF9 // XTAL/resonator
#define LP 0x3FF8 // low power XTAL/resonator#endif
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