Отправлено Elektronik 27 января 2004 г. 17:06 В ответ на: Если у Вас есть какой-нибудь код для примера - я бы посмотрел. А "мудреное" - понятие относительное. отправлено kolega 27 января 2004 г. 16:48

файл иницализации
start167

; BUSCON3/ADDRSEL3
; --- Set BUSCON3 = 1 to initialize the BUSCON3/ADDRSEL3 registers
$SET (BUSCON3 = 1)
;
; Define the start address and the address range of Chip Select 3 (CS3#) 
; This values are used to set the ADDRSEL3 register
%DEFINE (ADDRESS3) (80000H)     ; Set CS3# Start Address (default 300000H)
%DEFINE (RANGE3)   (64K)       ; Set CS3# Range (default 1024K = 1MB)
;  
; MCTC3: Memory Cycle Time (BUSCON3.0 .. BUSCON3.3):
; Note: if RDYEN3 == 1 a maximum number of 7 waitstates can be selected
_MCTC3	 EQU	13	; Memory wait states is 1 (MCTC3 field = 0EH).
;
; RWDC3: Read/Write Signal Delay (BUSCON3.4):
_RWDC3	 EQU	1	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; MTTC3: Memory Tri-state Time (BUSCON3.5):
_MTTC3	 EQU	1	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; BTYP3: External Bus Configuration Control (BUSCON3.6 .. BUSCON3.7):
_BTYP3	 EQU	2	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL3: ALE Lengthening Control Bit (BUSCON3.9):
_ALECTL3 EQU	0	; see data sheet for description
;
; BUSACT3: Bus Active Control Bit (BUSCON3.10):
_BUSACT3 EQU	1	; = 0 external (ADDRSEL3) bus disabled
			; = 1 external (ADDRSEL3) bus enabled
;
; RDYEN3: READY# Input Enable control bit (BUSCON3.12):
_RDYEN3  EQU	0	; 0 = READY# function disabled
;			; 1 = READY# function enabled
;
; RDY_AS3: Synchronous / Asynchronous READY# Input (BUSCON3.3):
; Note: This bit is only valid if _RDYEN3 == 1.
_RDY_AS3 EQU	0	; 0 = synchronous READY# input
;			; 1 = asynchronous READY# input
;
; CSREN3: Read Chip Select Enable bit (BUSCON3.14):
_CSREN3  EQU	0	; 0 = CS3# is independent of read command (RD#)
;			; 1 = CS3# is generated for the duration of read
;
; CSWEN3: Write Chip Select Enable bit (BUSCON3.15):
_CSWEN3  EQU	0	; 0 = CS3# is independent of write command (WR#)
;			; 1 = CS3# is generated for the duration of write
;
;

/* ADC and DAC on Cascod's controller */
#define CAS_ADC HVAR(unsigned int,   0x80000)
#define CAS_C_DAC HVAR(unsigned int, 0x80300)
#define CAS_1_DAC HVAR(unsigned int, 0x80400)
#define CAS_2_DAC HVAR(unsigned int, 0x80402)
#define CAS_3_DAC HVAR(unsigned int, 0x80404)
#define CAS_4_DAC HVAR(unsigned int, 0x80406)

CAS_1_DAC = cod1;  // Запись в первый канал
CAS_2_DAC = cod2;
CAS_3_DAC = cod3;
CAS_4_DAC = cod4;  // Запись в 4-й канал
CAS_C_DAC = 0;