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The Bit Clock pin, which determines the
data shift rate for `B' and `D' channel data
on the digital interface side of the device.
When Digital System Interface (DSI) Slave
mode is selected (see Digital Interfaces
section), BCLK is an input which may be
any multiple of 8 kHz from 256 kHz to
4.096 MHz. It need not be synchronous
with MCLK.
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