Отправлено Ashr 15 января 2003 г. 11:27 В ответ на: Подскажите... SPI на ADuC812... Очень надо :-| отправлено Dmitry... 15 января 2003 г. 09:40

Это из Errata Sheet.

4. SPI FUNCTION - OPERATION OF THE SPI INTERRUPT BIT ISPI :

Background:
The SPI Interrupt bit ISPI in the SPI Control SFR (SPICON) is set at the end of an SPI transfer (8 SPI Clocks). Typically this bit can be used in an interrupt driven routine to vector to the SPI Interrupt Vector Address at 003BH. Alternatively this bit can be polled in software to detect a new reception or completion of a byte еansmission.

Issue:
In an interrupt driven routine this bit is automatically cleared when the PC vectors to the SPI ISR. However, in a polled implementation the bit is not writable and is not cleared on subsequent accesses to the SPI data SFRs. This means that in a software polled scheme the ISPI bit is set after the first transmission but will not and cannot be cleared for subsequent byte communications which can result in subsequent reads of the same initial byte or corruption of a byte transmission before it is completed.

Work-Around :
a. Use the SPI peripheral in interrupt driven mode only, thereby avoiding any issues with the ISPI bit as this bit is automatically set and cleared in an SPI interrupt driven routine.

b. In master mode SPI operation, use dummy ‘NOP’ instructions to time
out a complete SPI 8-Clock cycle before trying to access the SPI data
SFRs.

5. SPI FUNCTION - SLAVE MODE FUNCTIONALITY :

Background:
In synchronous slave mode (CPOL=0/1, CPHA=0) the new MSB output
value appears on MISO when ~SS goes low.

Issue:
The SPI slave does not function correctly as a transmitter in modes 00 and 10 (i.e. when CPHA=0). The MSB of the transmitted byte is corrupted by the MSB of the byte just received.

Work-Around :
To transmit in Slave mode use the alternate SPI Slave operating mode
(CPOL=0/1, CPHA=1).