Отправлено Gosha 30 августа 2002 г. 12:00 В ответ на: Подскажите, где бы описание Манчестера найти? Спасибо. отправлено HoBo 29 августа 2002 г. 21:08

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A Manchester Encoder

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/******************************************************************************
*
* AUTHOR: Celia Clause
*-------------------------
* Copyright September 1997
*
********************************************************************************
* REVISION HISTORY
* ----------------
* $Revision$
* $Log$
*
********************************************************************************
*
* Module Manchester Encoder-- A number of differnet techniques for encoding
* data on a magnetic disk have been developed over the years. One popular
* scheme is known as phase encoding or Manchester encoding. In this scheme,
* changes in magnetization occur for each data bit. A change of
* magnetization is guaranteed at the midpoint of each bit period, the
* providing clocking information for the heads. The drowback of Manchester
* encoding is its poor bit-storage density. The space required to represent
* each bit must be large enough to accoummodate two changes in
* magnetization.
*
* _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
* clk _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|
* ___ ___ ___ ___ ___ ___ ___ ___
* phase _/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___
* ___ _______ ___ ___ ___ _______
* enc_data _____/ \___/ \___/ \___/ \_______/ \___/ \___
* | | | | | | |
* | 0 | 1 | 1 | 1 | 0 | 0 | 1
* _______
* data_load _/ \_______________________________________________________
*
*
******************************************************************************/
module manch_enc (enc_data, enc_ready, clk, reset, data_load, data);

parameter BIT_WIDTH = 8;

output enc_data;
output enc_ready;
input clk;
input reset;
input data_load;
input [BIT_WIDTH - 1:0] data;

reg phase;
reg busy;
wire enc_data;
wire enc_ready;
reg [2:0] bit_count;
reg [BIT_WIDTH - 1:0] reg_data;
integer i;

/***********************************************************
Generate a phase pulse to keep track of which cycle data
is high and which cycle data is low
************************************************************/

always @ (posedge clk)
begin
if (reset) begin
phase <= 0;
end
else begin
phase <= ~phase;
end
end

/*************************************************************
Load the byte wide input register if the data_load flag is
true and we are in the first phase and the last byte has been
shifted out. (Busy is false)
**************************************************************/

always @ (posedge clk)
begin
if (phase & data_load & !busy) begin
reg_data <= data;
end
end

/***************************************************************
The encoder is busy if the register has been loaded and we
haven't shifted out eight bits of data (Ready is true if we
are not busy
****************************************************************/
always @ (posedge clk)
begin
if (reset) begin
busy <= 0;
end
else if (data_load & phase) begin
busy <= 1;
end
else if ((bit_count == BIT_WIDTH - 1) && phase) begin
busy <= 0;
end
end

assign enc_ready = !busy;

/*****************************************************************
The bit count gets incremented if we are in the process of
shifting out data
******************************************************************/
always @ (posedge clk)
begin
if (reset) begin
bit_count <= 0;
end
else if (phase & busy) begin
bit_count <= bit_count + 1;
end
end

/******************************************************************
At each new phase, shift out a new bit of data. If shift out the
bit value during the time phase is high otherwise shift out the
inverse of the data when phase is low
*******************************************************************/
always @ (posedge clk)
begin
if (phase & busy) begin
reg_data[7:0] <= {1'b0,reg_data[7:1]};
end
end

assign enc_data = reg_data[0] ^ phase;

endmodule //of manch_enc

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