• ARM7TDMI-S processor, running at up to 72 MHz.
• Up to 512 kB on-chip Flash Program Memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Single Flash sector or full-chip erase in
400 ms and 256 bytes programming in 1 ms. Flash program memory is on the ARM
local bus for high performance CPU access.
• Up to 64 kB of SRAM on the ARM local bus for high performance CPU access.
• 16 kB Static RAM for Ethernet interface. Can also be used as general purpose SRAM.
• 8 kB Static RAM for general purpose or USB interface.
• Dual AHB system that provides for simultaneous Ethernet DMA, USB DMA, and
program execution from on-chip flash with no contention between those functions. A
bus bridge allows the Ethernet DMA to access the other AHB subsystem.
• Advanced Vectored Interrupt Controller, supporting up to 32 vectored interrupts.
• General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I
2S port, and the SD/MMC card port, as well as for
memory-to-memory transfers.
• Serial Interfaces:
– Ethernet MAC with associated DMA controller. These functions reside on an
independent AHB bus.
– On LPC2364/66/68, LPC2378, LPC2387, LPC2388: USB 2.0 device controller
with on-chip PHY and associated DMA controller.
– On LPC2388: USB Host/OTG controller.
– Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO. These reside on the APB bus.
– SPI controller, residing on the APB bus.
– Two SSP controllers with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. The SSP controllers can be used with the
GPDMA controller and reside on the APB bus.
– Three I
2C interfaces reside on the APB bus. The second and third I
2C interfaces
are expansion I
2C interfaces with standard port pins rather than special open-drain
I
2C pins.
– I
2S (Inter-IC Sound) interface for digital audio input or output, residing on the APB
bus. The I
2S interface can be used with the GPDMA.
– On LPC2364/66/68, LPC2378, LPC2387, LPC2388: Two CAN channels with
Acceptance Filter/FullCAN mode residing on the APB bus.
• Other APB Peripherals:
– On LPC2367/68, LPC2377/78, LPC2387, LPC2388: Secure Digital (SD) /
MultiMediaCard (MMC) memory card interface.
– Up to 70 (100 pin packages) or 104 (144 pin packages) general purpose I/O pins.
– 10 bit A/D converter with input multiplexing among 6 pins (100 pin packages) or 8
pins (144 pin packages).
– 10 bit D/A converter.
– Four general purpose timers with two capture inputs each and up to four compare
output pins each. Each timer block has an external count input.
– One PWM/Timer block with support for three-phase motor control. The PWM has
two external count inputs.
– Real-Time Clock (RTC) with separate power pin; clock source can be the RTC
oscillator or the APB clock.
– 2 kB Static RAM powered from the RTC power pin, allowing data to be stored
when the rest of the chip is powered off.
– Watchdog Timer. The watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator, or the APB clock.
• Standard ARM Test/Debug interface for compatibility with existing tools.
Emulation Trace Module.
• Support for real-time trace.
• Single 3.3 V power supply (3.0 V to 3.6 V).
• Three reduced power modes: Idle, Sleep, and Power-down.
• Four external interrupt inputs. In addition every PORT0/2 pin can be configured as an
edge sensing interrupt.
• Processor wakeup from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, and Ethernet wakeup
interrupt).
• Two independent power domains allow fine tuning of power consumption based on
needed features.
• Brownout detect with separate thresholds for interrupt and forced reset.
• On-chip Power On Reset.
• On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
• 4 MHz internal RC oscillator that can optionally be used as the system clock. For USB
and CAN application, the use of an external clock source is suggested.
• On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
• Boundary scan for simplified board testing is available in LPC2364FET100,
LPC2368FET100 (TFBGA packages), LPC2377/78, and LPC2388.
• Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.