Since the AD7705/AD7706 contains this on-chip, low-pass
filtering, a settling time is associated with step function inputs
and data on the output will be invalid after a step change until
the settling time has elapsed. The settling time depends upon
the output rate chosen for the filter. The settling time of the
filter to a full-scale step input can be up to four times the output
data period. For a synchronized step input (using the FSYNC
function), the settling time is three times the output data period.