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Latest "Electronic Design":
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Although the C8051F120 MCU core operates at 100 MHz,
its flash memory is limited to 25 MHz. This isn’t an issue,
however, because of the prefetch queue and cache that Cygnal
put in the design. Essentially, the flash is read in 32-bit words
(4 instruction bytes) at 25-MHz speeds, and the instruction
decode is fed 8-bit bytes at 100 MHz. Most instructions are 1
or 2 bytes, achieving 100-MIPS performance (Fig. 2).
For sequential program execution, the prefetch buffer is
deployed. If the next instruction is out of sequence due to a
jump or call, then the cache is checked. When available, the
cache word containing the instruction is used, with subse-quent
words ac-essed through the prefetch queue.
This means that the cache only needs to hold single words,
rather than entire sequences of instructions as in a typical
instruction cache. Very tight loops may be maintained within
the cache. But only the first few instructions are necessary.
However, if the next instruction is not in the cache, a delay
occurs until the required word is read from flash. The typical
cache hit rate is above 90%. Both cache operation and hard-ware
debug support are transparent to the software.
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C8051F120 will be sampled in June, with production slated for the third
quarter. The C8051F120 comes in a 100-pin TQFP, and the C8051F121
is housed in a 64-pin TQFP package. In 1000-piece quantities, the
C8051F120 and C8051F121 are priced at $18.75 and $17.82.
A development kit is in preparation too, including a development
board, all IDE software, evaluation C compiler, and RS-232 to JTAG serial
adapter. It will be available in June as well for $149.00.
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E-mail: 
info@telesys.ru
