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.include "2313def.inc".def tmp =r16 ;register for temporary storage
.def tmp1 =r17 ;register for temporary storage
.def instr =r18 ;here request code will be stored.cseg
.org 0x0000
rjmp start ;Reset handler
.org URXCaddr ;UART Receive Complete Interrupt Vector Address
rjmp urxc_int
;******************************************************************
; INTERRUPTS HANDLERS
;******************************************************************
; UART INTERRUPT
;******************************************************************
urxc_int:
in tmp, SREG
push tmp
in instr,UDR
urxc_int_exit:
pop tmp
out SREG, tmp
reti
;******************************************************************
SendChar: ;transmits byte from r0
;destroys:r0
in tmp1,USR;check UDRE bit in USR register and skip if set
sbrs tmp1,UDRE
rjmp SendChar
out UDR,tmp
retSend_ask:
ldi tmp, '?'
rcall SendChar
rjmp Send_CRLF
Send_Pl:
ldi tmp, '+'
rcall SendChar
Send_CRLF:
ldi tmp, 0x0d
rcall SendChar
ldi tmp, 0x0a
rcall SendChar
ret
;******************************************************************
; INITIALIZATION
;******************************************************************
uart_init:
ldi tmp,0x98 ;rxc int enabled, tx & rx enabled
out UCR,tmp
ldi tmp,25 ;9600 @ 4 Mhz XTAL
out UBRR,tmp
ret
;******************************************************************
;****** S T A R T ***********************************************
;******************************************************************
start:
ldi tmp,RAMEND ;init SP
out SPL,tmpclr tmp
out DDRB,tmp ;Set port B as imput w/o pullup
out PORTB,tmprcall uart_init ;Init UART
sei ;Enable interrupts
ldi instr, 0
main_loop:
tst instr
breq main_loop
cpi instr, '0'
breq Instr_I
cpi instr, '1'
breq Instr_I
cpi instr, '2'
breq Instr_I
cpi instr, '3'
breq Instr_I
cpi instr, '4'
breq Instr_I
cpi instr, '5'
breq Instr_I
cpi instr, '6'
breq Instr_I
cpi instr, '7'
breq Instr_I
cpi instr, '8'
breq Instr_I
cpi instr, '9'
breq Instr_I
rcall Send_ask
end_ins:
ldi instr, 0
rjmp main_loop
Instr_I:
rcall Send_Pl
rjmp end_ins
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