out SPSR,temp ;double SPI speed ldi temp,100
rcall mDel ;FPGA power-up delay 100 mS
Port_NCLR_1 ;release nCLR
ret
;----------------------------------------------------------------------------
;Set configuration mode for FPGA:
FPGA_SetCfg:
Port_nCONFIG_0 ;nCONFIG <- 0
ldi Cnt,100
rcall uDel ;delay 100 uS
Port_nCONFIG_1 ;nCONFIG <- 1
ldi Cnt,100
rcall uDel ;delay 100 uS
ret
;----------------------------------------------------------------------------
;Tx FPGA configuration data byte:
;Input: Y - pointer to configuration data (uncrypted)
; Cnt - number of bytes
;Out: temp - status: 0 - OK, 1 - Done, 2 - Error
FPGA_TxCfg:
next_b: ld temp,Y+
rcall Spi_WR ;write configuration byte
Skip_if_nSTAT_1
rjmp cfg_err
Skip_if_CONFD_0
rjmp cfg_done
dec Cnt
brne next_b
ldi temp,0 ;configuration in progress
rjmp cfg_r
cfg_done:
ldi Cnt,100
rcall uDel ;delay 100 uS
ldi temp,1 ;configuration done
rjmp cfg_r
cfg_err:
ldi temp,2 ;configuration error
cfg_r: ret
;----------------------------------------------------------------------------
;Write/Read byte via SPI:
;Input: temp - data byte to transmit
;Out: temp - recieved data byte
Spi_WR: out SPDR,temp
spwait: sbis SPSR,SPIF
rjmp spwait
in temp,SPDR
ret
