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46 GRPCI - PCI Target / Master Unit
46.1 Overview
The PCI Target/Master Unit is a bridge between PCI bus and AMBA AHB bus. The unit is connected
to the PCI bus through two interfaces PCI Target and PCI Master. PCI Master interface is optional and
can be disabled in the VHDL model. Two interfaces connect the core to the AHB bus: AHB Slave and
AHB Master Interface. PCI Configuration / Status register is attached to AMBA APB bus.
The PCI and AMBA interfaces belong to two different clock domains. Synchronization is performed
inside the core through FIFOs with configurable depth.
The DMA controller is set up by defining the location of memory areas between which the DMA will
take place in both PCI and AHB address space as well as direction, length and type of the transfer.
Only 32-bit word transfer are supported.
The DMA transfer is automatically aborted when any kind of error is detected during a transfer. The
DMA controller does not detect deadlocks in its communication channels. If the system concludes
that a deadlock has occurred, it can manually abort the DMA transfer. It is allowed to perform burst
over a 1 Kbyte boundary of the AHB bus. When this happens, an AHB idle cycle will be automatically
inserted to break up the burst over the boundary.
When the DMA is not active the AHB slave interface of PCI Master/Target unit will be directly connected
to AMBA AHB bus.
PCITARGET - Simple 32-bit PCI target with AHB interface
48.1 Overview
This core implements PCI interface with a simple target-only interface. The interface is developed
primarily to support DSU communication over the PCI bus. Focus has been put on small area and
robust operation, rather than performance. The interface has no FIFOs, limiting the transfer rate to
about 5 Mbyte/s. This is however fully sufficient to allow fast download and debugging using the
DSU.
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