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/****************************************************************************
** - iom8515.h -
**
** This file declares the internal register addresses for ATmega8515.
**
** Used with iccAVR and aAVR.
**
** Copyright IAR Systems 2002. All rights reserved.
**
** File version: $Revision: 1.7 $
**
***************************************************************************/#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif#include "iomacro.h"
#if TID_GUARD(1)
#error This file should only be compiled with iccavr or aavr with processor option -v1
#endif /* TID_GUARD(1) *//* Include the SFR part if this file has not been included before,
* OR this file is included by the assembler (SFRs must be defined in
* each assembler module). */
#if !defined(__IOM8515_H) || defined(__IAR_SYSTEMS_ASM__)#pragma language=extended
/*==========================*/
/* Predefined SFR Addresses */
/*==========================*//****************************************************************************
* An example showing the SFR_B() macro call,
* the expanded result and usage of this result:
*
* SFR_B(AVR, 0x1F) Expands to:
* __io union {
* unsigned char AVR; // The sfrb as 1 byte
* struct { // The sfrb as 8 bits
* unsigned char AVR_Bit0:1,
* AVR_Bit1:1,
* AVR_Bit2:1,
* AVR_Bit3:1,
* AVR_Bit4:1,
* AVR_Bit5:1,
* AVR_Bit6:1,
* AVR_Bit7:1;
* };
* } @ 0x1F;
* Examples of how to use the expanded result:
* AVR |= (1<<5);
* or like this:
* AVR_Bit5 = 1;
***************************************************************************/SFR_B(OSCCAL, 0x04) /* Oscillator Calibration Register */
SFR_B(PINE, 0x05) /* Port E Input Pins Address */
SFR_B(DDRE, 0x06) /* Port E Data Direction Register */
SFR_B(PORTE, 0x07) /* Port E Data Register */
SFR_B(ACSR, 0x08) /* Analog Comparator Control and Status Register */
SFR_B(UBRRL, 0x09) /* USART Baud Rate Register Low */
SFR_B(UCSRB, 0x0A) /* USART Control and Status Register B */
SFR_B(UCSRA, 0x0B) /* USART Control and Status Register A */
SFR_B(UDR, 0x0C) /* USART I/O Data Register */
SFR_B(SPCR, 0x0D) /* SPI Control Register */
SFR_B(SPSR, 0x0E) /* SPI Status Register */
SFR_B(SPDR, 0x0F) /* SPI Data Register */
SFR_B(PIND, 0x10) /* Port D Input Pins Address */
SFR_B(DDRD, 0x11) /* Port D Data Direction Register */
SFR_B(PORTD, 0x12) /* Port D Data Register */
SFR_B(PINC, 0x13) /* Port C Input Pins Address */
SFR_B(DDRC, 0x14) /* Port C Data Direction Register */
SFR_B(PORTC, 0x15) /* Port C Data Register */
SFR_B(PINB, 0x16) /* Port B Input Pins Address */
SFR_B(DDRB, 0x17) /* Port B Data Direction Register */
SFR_B(PORTB, 0x18) /* Port B Data Register */
SFR_B(PINA, 0x19) /* Port A Input Pins Address */
SFR_B(DDRA, 0x1A) /* Port A Data Direction Register */
SFR_B(PORTA, 0x1B) /* Port A Data Register */
SFR_B(EECR, 0x1C) /* EEPROM Control Register */
SFR_B(EEDR, 0x1D) /* EEPROM Data Register */
SFR_W(EEAR, 0x1E) /* EEPROM Address Register */
SFR_B2(UBRRH, UCSRC, 0x20)
/* USART Baud Rate Register 0 High */
/* USART Control and Status Register 0 C */
SFR_B(WDTCR, 0x21) /* Watchdog Timer Control Register */
SFR_W(ICR1, 0x24) /* Timer/Counter1 Input Capture Register */
SFR_W(OCR1B, 0x28) /* Timer/Counter1 Output Compare Register B */
SFR_W(OCR1A, 0x2A) /* Timer/Counter1 Output Compare Register A */
SFR_W(TCNT1, 0x2C) /* Timer/Counter1 */
SFR_B(TCCR1B, 0x2E) /* Timer/Counter1 Control Register B */
SFR_B(TCCR1A, 0x2F) /* Timer/Counter1 Control Register A */
SFR_B(SFIOR, 0x30) /* Special Function IO Register */
SFR_B(OCR0, 0x31) /* Timer/Counter0 Output Compare Register */
SFR_B(TCNT0, 0x32) /* Timer/Counter0 */
SFR_B(TCCR0, 0x33) /* Timer/Counter0 Control Register */
SFR_B(MCUCSR, 0x34) /* MCU Control and Status Register */
SFR_B(MCUCR, 0x35) /* MCU Control Register */
SFR_B(EMCUCR, 0x36) /* Extended MCU Control Register */
SFR_B(SPMCR, 0x37) /* Store Program Memory Control Register */
SFR_B(TIFR, 0x38) /* Timer/Counter Interrupt Flag Register */
SFR_B(TIMSK, 0x39) /* Timer/Counter Interrupt Mask Register */
SFR_B(GIFR, 0x3A) /* General Interrupt Flag Register */
SFR_B(GICR, 0x3B) /* General Interrupt Control Register */
SFR_W(SP, 0x3D) /* Stack Pointer */
SFR_B(SREG, 0x3F) /* Status Register */#ifndef __IOM8515_H
#define __IOM8515_H/* SFRs are local in assembler modules (so this file may need to be */
/* included in more than one module in the same source file), */
/* but #defines must only be made once per source file. *//*==============================*/
/* Interrupt Vector Definitions */
/*==============================*//* NB! vectors are specified as byte addresses */
#define RESET_vect (0x00)
#define INT0_vect (0x02)
#define INT1_vect (0x04)
#define TIMER1_CAPT_vect (0x06)
#define TIMER1_COMPA_vect (0x08)
#define TIMER1_COMPB_vect (0x0A)
#define TIMER1_OVF_vect (0x0C)
#define TIMER0_OVF_vect (0x0E)
#define SPI_STC_vect (0x10)
#define USART_RXC_vect (0x12)
#define USART_UDRE_vect (0x14)
#define USART_TXC_vect (0x16)
#define ANA_COMP_vect (0x18)
#define INT2_vect (0x1A)
#define TIMER0_COMP_vect (0x1C)
#define EE_RDY_vect (0x1E)
#define SPM_RDY_vect (0x20)
#ifdef __IAR_SYSTEMS_ASM__
#ifndef ENABLE_BIT_DEFINITIONS
#define ENABLE_BIT_DEFINITIONS
#endif /* ENABLE_BIT_DEFINITIONS */
#endif /* __IAR_SYSTEMS_ASM__ */#ifdef ENABLE_BIT_DEFINITIONS
/* Bit definitions for use with the IAR Assembler
The Register Bit names are represented by their bit number (0-7). *//* Port E Input Pins Address - PINE */
#define PINE2 2
#define PINE1 1
#define PINE0 0/* Port E Data Direction Register - DDRE */
#define DDE2 2
#define DDE1 1
#define DDE0 0/* Port E Data Register - PORTE */
#define PE2 2
#define PE1 1
#define PE0 0/* Port E Data Register - PORTE */
#define PORTE2 2
#define PORTE1 1
#define PORTE0 0/* Analog Comparator Control and Status Register - ACSR */
#define ACD 7
#define ACBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0/* USART Control and Status Register B - UCSRB */
#define RXCIE 7
#define TXCIE 6
#define UDRIE 5
#define RXEN 4
#define TXEN 3
#define UCSZ2 2
#define RXB8 1
#define TXB8 0/* USART Control and Status Register A - UCSRA */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
#define PE 2
#define U2X 1
#define MPCM 0/* SPI Control Register - SPCR */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0/* SPI Status Register - SPSR */
#define SPIF 7
#define WCOL 6
#define SPI2X 0/* Port D Input Pins Address - PIND */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0/* Port D Data Direction Register - DDRD */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* Port D Data Register - PORTD */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* Port D Data Register - PORTD */
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* Port C Input Pins Address - PINC */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0/* Port C Data Direction Register - DDRC */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* Port C Data Register - PORTC */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* Port C Data Register - PORTC */
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
/* Port B Input Pins Address - PINB */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0/* Port B Data Direction Register - DDRB */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0/* Port B Data Register - PORTB */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0/* Port B Data Register - PORTB */
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0/* Port A Input Pins Address - PINA */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0/* Port A Data Direction Register - DDRA */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0/* Port A Data Register - PORTA */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0/* Port A Data Register - PORTA */
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0/* EEPROM Control Register - EECR */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0/* USART Baud Rate Register 0 High - UBRR0H and
USART Control and Status Register 0 C - UCSR0C */
#define URSEL 7
#define UMSEL 6
#define UPM1 5
#define UPM0 4
#define USBS 3
#define UCSZ1 2
#define UCSZ0 1
#define UCPOL 0/* Watchdog Timer Control Register - WDTCR */
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0/* Timer/Counter1 Control Register B - TCCR1B */
#define ICNC1 7
#define ICES1 6
#define WGM13 4
#define WGM12 3
#define CS12 2
#define CS11 1
#define CS10 0/* Timer/Counter1 Control Register A - TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define FOC1A 3
#define FOC1B 2
#define WGM11 1
#define WGM10 0
/* Special Function IO Register - SFIOR */
#define XMBK 6
#define XMM2 5
#define XMM1 4
#define XMM0 3
#define PUD 2
#define PSR10 0
/* Timer/Counter0 Control Register - TCCR0 */
#define FOC0 7
#define WGM00 6
#define COM01 5
#define COM00 4
#define WGM01 3
#define CS02 2
#define CS01 1
#define CS00 0/* MCU Control and Status Register - MCUCSR */
#define SM2 5
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* MCU Control Register - MCUCR */
#define SRE 7
#define SRW10 6
#define SE 5
#define SM1 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0/* Extended MCU Control Register - EMCUCR */
#define SM0 7
#define SRL2 6
#define SRL1 5
#define SRL0 4
#define SRW01 3
#define SRW00 2
#define SRW11 1
#define ISC2 0/* Store Program Memory Control Register - SPMCR */
#define SPMIE 7
#define RWWSB 6
#define RWWSRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0/* Timer/Counter Interrupt Flag Register - TIFR */
#define TOV1 7
#define OCF1A 6
#define OCF1B 5
#define ICF1 3
#define TOV0 1
#define OCF0 0/* Timer/Counter Interrupt Mask Register - TIMSK */
#define TOIE1 7
#define OCIE1A 6
#define OCIE1B 5
#define TICIE1 3
#define TOIE0 1
#define OCIE0 0/* General Interrupt Flag Register - GIFR */
#define INTF1 7
#define INTF0 6
#define INTF2 5
/* General Interrupt Control Register - GICR */
#define INT1 7
#define INT0 6
#define INT2 5
#define IVSEL 1
#define IVCE 0
/* USART Baud Rate Register 1 High - UBRR1H and
USART Control and Status Register 1 C - UCSR1C */
#define URSEL1 7
#define UMSEL1 6
#define UPM11 5
#define UPM10 4
#define USBS1 3
#define UCSZ11 2
#define UCSZ10 1
#define UCPOL1 0/* Pointer definition */
#define XL R26
#define XH R27
#define YL R28
#define YH R29
#define ZL R30
#define ZH R31
/* Constants */
#define RAMEND 0x25F /* Last On-Chip SRAM Location */
#define XRAMEND 0xFFFF
#define E2END 0x1FF
#define FLASHEND 0x1FFF#endif /* ENABLE_BIT_DEFINITIONS */
#endif /* __IOM8515_H (define part) */#pragma language=default
#endif /* __IOM8515_H (SFR part) */
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