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reg [2:0] divider;always @(posedge clock) if (divider[2]) divider <= 3'h0; else divider <= divider + 1'b1;assign out = divider[1];
always @(posedge clock) if (divider[2]) divider <= 3'h0; else divider <= divider + 1'b1;
assign out = divider[1];