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17.1.1 Overview
A multi-function external bus interface called the FlexBus interface controller is provided on the
MCF548x with basic functionality of interfacing to slave-only devices up to a maximum bus frequency of
66 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot
ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional
circuitry. For asynchronous devices a simple chip-select based interface can be used.
The FlexBus interface has six general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be
dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32
bits) wide. Control signal timing is compatible with common ROM / flash memories.
17.5 Chip-Select Operation
Each chip-select has a dedicated set of the following registers for configuration and control:
• Chip-select address registers (CSARn) control the base address space of the chip-select. See
Section 17.5.2.1, “Chip-Select Address Registers (CSAR0–CSAR5).”
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See
Section 17.5.2.2, “Chip-Select Mask Registers (CSMR0–CSMR5).”
• Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state
generation, address setup and hold times, and automatic acknowledge generation features. See
Section 17.5.2.3, “Chip-Select Control Registers (CSCR0–CSCR5).”
FBCS0 is a global chip-select after reset and provides re-locatable boot ROM capability.
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