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To better understand the interrupt priority structure, consider a simple example with nested interrupts.
Assume that the following have already taken place:
1. A serial port on a chip has requested a level 1 interrupt when the core’s CCPL was at level 0.
2. The core has recognized this interrupt and entered the exception processing state. The CCPL was updated from level 0 to level 2, which is one level higher than the priority of the recognized interrupt level 1).
3. Program flow has been transferred to the interrupt handler for the serial port.
Now consider that a second peripheral, a timer with interrupt priority level 0, generates an interrupt.
Although the interrupt request is valid, the interrupt will not be acknowledged and serviced because the peripheral’s priority level is lower than the core’s CCPL. If the interrupt request can be latched as pending, the interrupt will be serviced after the current interrupt service routine completes, because the CCPL will be restored to its original level (level 0). A higher-priority interrupt (at level 2, for instance) would interrupt the level 1 service routine, and the level 1 routine would resume later after the level 2 handler completed.
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