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MEMMAP = 1;
// PLL Example:
// System design asks for Fosc= 10 MHz and requires cclk = 60 MHz.
// Based on these specifications, M = cclk / Fosc = 60 MHz / 10 MHz = 6.
// Consequently, M-1 = 5 will be written as PLLCFG 4:0.
// Value for P can be derived from P = Fcco / (cclk * 2), using condition
// that Fcco must be in range of 156 MHz to 320 MHz. Assuming
// the lowest allowed frequency for Fcco = 156 MHz, P = 156 MHz / (2*60 MHz) = 1.3.
// The highest Fcco frequency criteria produces
// P = 2.67. The only solution for P that satisfies both of these
// requirements and is listed in Table 20 is P = 2. Therefore, PLLCFG
// 6:5 = 1 will be used.
PLL2138->PLLCON = 1;
PLL2138->PLLCFG = 0x25;
PLL2138->PLLFEED = 0xAA;
PLL2138->PLLFEED = 0x55;
do {} while (!(PLL2138->PLLSTAT & (1 << 10)));
PLL2138->PLLCON = 3;
PLL2138->PLLFEED = 0xAA;
PLL2138->PLLFEED = 0x55;
MAM2138->MAMCR = 0;
MAM2138->MAMTIM = 3;
MAM2138->MAMCR = 2;
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