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ENTIRE COMMAND SEQUENCE FOR 5 MHz PROGRAM
0xF800 Binary (1111 1000 0000 0000)
0x3333 Binary (0011 0011 0011 0011)
0x2233 Binary (0010 0010 0011 0011)
0x3133 Binary (0011 0001 0011 0011)
0x2033 Binary (0010 0000 0011 0011)
0xC000 Binary (1100 0000 0000 0000)
COMMAND SEQUENCE EXPLAINED
For the purpose of this explanation, the 16-bit SPI word will be addressed as follows:
D15, D14, D13, ..., D2, D1, D0
0xF800 Binary (1111 1000 0000 0000)
D15, D14 = 1,1. This means that bits D13, D12, and D11 are active. In this case:
D13 = 1, SLEEP bit. This puts the part into sleep mode.
D12 = 1, RESET bit. This sets the part into reset, i.e., output of the DAC will be midscale.
D11 = 1, CLR bit. When CLR = 1, SYNC and SELSRC are set to 1. This sets control of choosing which register is selected to
external pins, not through software. CLR will automatically reset to 0.
D10...D0 = 0. (These are Don’t Care bits, X.)
The part is now ready to be programmed.
0x3333 Binary (0011 0011 0011 0011)
Command broken down as follows:
0011 /* Write eight frequency bits to defer register */
0011 /* Write to Frequency 0 Reg, H MSBs */
0011 0011 /* Eight bits of data to write */
0x2233 Binary (0010 0010 0011 0011)
0010 /* Write eight frequency bits to defer register */
0010 /* Write to Frequency 0 Reg, L MSBs */
0011 0011 /* Eight bits of data to write */
16 bits are now loaded to the upper 16 bits of Frequency Register 0.
0x3133 Binary (0011 0001 0011 0011)
0011 /* Write eight frequency bits to defer register */
0001 /* Write to Frequency 0 Reg, H LSBs */
0011 0011 /* Eight bits of data to write */
0x2033 Binary (0010 0000 0011 0011)
0010 /* Write eight frequency bits to defer register */
0000 /* Write to Frequency 0 Reg, L LSBs */
0011 0011 /* Eight bits of data to write */
16 bits are now loaded to the lower 16 bits of Frequency Register 0.
0xC000 Binary (1100 0000 0000 0000)
D15, D14 = 1,1. This means that bits D13, D12, and D11 are active. In this case:
D13 = 0, SLEEP bit. Takes the part out of sleep mode.
D12 = 0, RESET bit. Takes the part out of reset mode.
D11 = 0, CLR bit.
D10...D0 = 0 (Don’t Care bits for this command.)
5 MHz will now appear on the output pin. The FSELECT pin must be pulled to GND to choose Frequency Reg 0.
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