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#include __CONFIG(1,HS+OSCSDIS); __IDLOC(0x2046000); The PLL is one of the modes of the FOSC<2:0> configuration 111 = RC oscillator w/ OSC2 configured as RA6
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__CONFIG(2,PWRTEN+BORV45+BORDIS+WDTDIS+WDTPS128);
__CONFIG(3,CCP2RC1);
__CONFIG(4,STVRDIS+LVPDIS+DEBUGDIS);
// __CONFIG(5,CPA+CPD+CPB); // code protect all
// __CONFIG(6,WPALL);
// __CONFIG(7,TRPALL);
The PLL can only be enabled when the oscillator configuration
bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
bits. The Oscillator mode is specified during
device programming.
bit 2-0 FOSC2:FOSC0: Oscillator Selection bits
110 = HS oscillator with PLL enabled/Clock frequency = (4 x FOSC)
101 = EC oscillator w/ OSC2 configured as RA6
100 = EC oscillator w/ OSC2 configured as divide-by-4 clock output
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
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