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Вот ассемблерный текст. На С сам перепиши, мне лень:
.nolist
.include "2313def.inc"
.list
.equ xtal = 10000000 ;XTAL frequency, Hz
.equ clktime = 30 ;CLK half cycle length, uS
.equ gaptime = 10000 ;Inter-packet gap length, uS
.equ sendlen = 11 ;Send packet length, CLK pulses
.equ clkpin = PORTD6 ;Define port pin used as CLK
.def temp = r16 ;8-bit working register
.def cntrl = r24 ;16-bit counter
.def cntrh = r25 ;
.cseg
ldi temp,RAMEND ;Initialize stack pointer
out spl,temp ;
cbi PORTD,clkpin ;Initialize CLK pin to logic "0"
ldi r16,1 << clkpin ;Configure CLK pin as output
out DDRD,r16 ;
main:
ldi temp,sendlen ;Initialize packet clock counter
send:
ldi cntrl,low((clktime*xtal)/10000000)
ldi cntrh,high((clktime*xtal)/10000000)
sbi PORTD,clkpin ;Set CLK pin to logic "1"
rcall delay ;Hold it in "1" for desired time
ldi cntrl,low((clktime*xtal)/10000000)
ldi cntrh,high((clktime*xtal)/10000000)
cbi PORTD,clkpin ;Set CLK pin to logic "0"
rcall delay ;Hold it in "0" for desired time
dec temp ;Repeat SENDLEN times
brne send ;
ldi cntrl,low(((gaptime-2*clktime*sendlen)*xtal)/10000000)
ldi cntrh,high(((gaptime-2*clktime*sendlen)*xtal)/10000000)
rcall delay ;Provide desired inter-packet delay
rjmp main ;Repeat forever
;Provides delay of approx. 10*cntr/xtal uS
delay:
nop
nop
nop
nop
nop
nop
sbiw cntrl,1 ;Decrement 16-bit delay counter
brpl delay ;Loop while it's still positive
ret
Вот НЕХ-файл, можешь прошить в МК (целых 58 байт:):
:020000020000FC
:100000000FED0DBF969800E401BB0BE08EE190E090
:10001000969A0AD08EE190E0969806D00A95B1F7AC
:100020008CE794E201D0F1CF000000000000000056
:0A003000000000000197C2F70895D8
:00000001FF
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