Отправлено Oleg_ 20 октября 2003 г. 20:25

Дано:
в synplify в отдельных проектах синтезированы файлы: a.vqm, b.vqm
в quartus созданы: проект1 ( a.vqm ) и проект2 ( a.vqm, b.vqm )

Проблема:
проект1 работает,
в проекте2 на стадии создания базы данных Quartus находит ошибку в файле a.vqm, которую не находит в проекте1

Вопрос:
Что делать ?

Cообшение Quartus:
Module Instantiation error: port q_a is in the named port connection list of a Module Instantiation,
but the port is not defined in the Module Declaration for instantiated module altsyncramZ0

Кусок файла a.vqm:

module altsyncramZ0 (
clock0,
clocken0,
address_a,
q_a
);
/* synthesis syn_black_box */

input clock0;
input clocken0;
input [7:0] address_a;
output [17:0] q_a;
altsyncram U1 (
.clock0(clock0),
.clocken0(clocken0),
.address_a(address_a),
.q_a(q_a)
);
defparam U1.width_a = 18;
defparam U1.widthad_a = 8;
defparam U1.numwords_a = 256;
defparam U1.outdata_reg_a = "UNREGISTERED";
defparam U1.address_aclr_a = "NONE";
defparam U1.outdata_aclr_a = "NONE";
defparam U1.indata_aclr_a = "NONE";
defparam U1.wrcontrol_aclr_a = "NONE";
defparam U1.byteena_aclr_a = "NONE";
defparam U1.width_byteena_a = 1;
defparam U1.width_b = 1;
defparam U1.widthad_b = 1;
defparam U1.numwords_b = 1;
defparam U1.rdcontrol_reg_b = "CLOCK1";
defparam U1.address_reg_b = "CLOCK1";
defparam U1.outdata_reg_b = "UNREGISTERED";
defparam U1.outdata_aclr_b = "NONE";
defparam U1.rdcontrol_aclr_b = "NONE";
defparam U1.indata_reg_b = "CLOCK1";
defparam U1.wrcontrol_wraddress_reg_b = "CLOCK1";
defparam U1.byteena_reg_b = "CLOCK1";
defparam U1.indata_aclr_b = "NONE";
defparam U1.wrcontrol_aclr_b = "NONE";
defparam U1.address_aclr_b = "NONE";
defparam U1.byteena_aclr_b = "NONE";
defparam U1.width_byteena_b = 1;
defparam U1.operation_mode = "ROM";
defparam U1.byte_size = 8;
defparam U1.read_during_write_mode_mixed_ports = "DONT_CARE";
defparam U1.ram_block_type = "M4K";
defparam U1.init_file = "mapper.hex";
defparam U1.init_file_layout = "UNUSED";
defparam U1.maximum_depth = 0;
defparam U1.intended_device_family = "Stratix";
defparam U1.lpm_hint = "UNUSED";
endmodule /* altsyncramZ0 */

......................

// @2:417
altsyncramZ0 mapper_i_u (
.clock0(clk),
.clocken0(VCC),
.address_a({alfa[1], alfa[0], mode[1], mode[0], mapp_q[6], mapp_q[4],
mapp_q[2], mapp_q[0]}),
.q_a({i[17], i[16], i[15], i[14], i[13], i[12], i[11], i[10], i[9], i[8],
i[7], i[6], i[5], i[4], i[3], i[2], i[1], i[0]})
);
// @2:417
altsyncramZ0 mapper_q_u (
.clock0(clk),
.clocken0(VCC),
.address_a({alfa[1], alfa[0], mode[1], mode[0], mapp_q[6], N_312_i, mapp_q[3],
mapp_q[1]}),
.q_a({q[17], q[16], q[15], q[14], q[13], q[12], q[11], q[10], q[9], q[8],
q[7], q[6], q[5], q[4], q[3], q[2], q[1], q[0]})
);
endmodule /* mapper */