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SUBDESIGN temp
(
clk : INPUT;
in[1..0] : INPUT;
sel : INPUT;
ena : INPUT;
out : OUTPUT;
)
VARIABLE
dffe_in : NODE;
BEGIN
IF sel THEN
dffe_in = in1;
ELSE
dffe_in = in0;
END IF;
out = DFFE (dffe_in, clk, VCC, VCC, ena);
END;
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