Отправлено miki 15 июля 2003 г. 13:34 В ответ на: Трудно что-то советовать, не видя текста и не зная для какой серии. отправлено KA 15 июля 2003 г. 12:42

Прошу прощения - семейство ProASIC Plus. Оставил только модуль SRAM,
результат тотже, Synplify устанавливает буферы IB22, OB33 - вроде все в порядке, но PAR не проходит.
Текст модуля VHDL(пробовал на Verilog - результат такой же):

library IEEE, APA;
use IEEE.std_logic_1164.all;

entity ram is

port(DO : out std_logic_vector (15 downto 0);
RCLOCK : in std_logic;
WCLOCK : in std_logic;
DI : in std_logic_vector (15 downto 0);
WRB : in std_logic;
RDB : in std_logic;
WADDR : in std_logic_vector (7 downto 0);
RADDR : in std_logic_vector (7 downto 0));

end ram;

architecture STRUCT_ram of ram is
component PWR
port(Y : out std_logic);
end component;

component GND
port(Y : out std_logic);
end component;

component RAM256x9SST
port(RCLKS : in std_logic;
WCLKS : in std_logic;
DO8 : out std_logic;
DO7 : out std_logic;
DO6 : out std_logic;
DO5 : out std_logic;
DO4 : out std_logic;
DO3 : out std_logic;
DO2 : out std_logic;
DO1 : out std_logic;
DO0 : out std_logic;
DOS : out std_logic;
WPE : out std_logic;
RPE : out std_logic;
WADDR7 : in std_logic;
WADDR6 : in std_logic;
WADDR5 : in std_logic;
WADDR4 : in std_logic;
WADDR3 : in std_logic;
WADDR2 : in std_logic;
WADDR1 : in std_logic;
WADDR0 : in std_logic;
RADDR7 : in std_logic;
RADDR6 : in std_logic;
RADDR5 : in std_logic;
RADDR4 : in std_logic;
RADDR3 : in std_logic;
RADDR2 : in std_logic;
RADDR1 : in std_logic;
RADDR0 : in std_logic;
DI8 : in std_logic;
DI7 : in std_logic;
DI6 : in std_logic;
DI5 : in std_logic;
DI4 : in std_logic;
DI3 : in std_logic;
DI2 : in std_logic;
DI1 : in std_logic;
DI0 : in std_logic;
WRB : in std_logic;
RDB : in std_logic;
WBLKB : in std_logic;
RBLKB : in std_logic;
PARODD : in std_logic;
DIS : in std_logic);
end component;

signal VDD, VSS, n1, n2, n3, n4, n5, n6, n7, n8 : std_logic;

begin

U1 : GND port map(Y => VSS);
M0 : RAM256x9SST port map(RCLKS => RCLOCK, WCLKS => WCLOCK, DO8 => DO(8), DO7 => DO(7), DO6 => DO(6),
DO5 => DO(5), DO4 => DO(4), DO3 => DO(3), DO2 => DO(2), DO1 => DO(1),
DO0 => DO(0), DOS => n1, WPE => n2, RPE => n3, WADDR7 => WADDR(7), WADDR6 => WADDR(6),
WADDR5 => WADDR(5), WADDR4 => WADDR(4), WADDR3 => WADDR(3), WADDR2 => WADDR(2),
WADDR1 => WADDR(1), WADDR0 => WADDR(0), RADDR7 => RADDR(7), RADDR6 => RADDR(6),
RADDR5 => RADDR(5), RADDR4 => RADDR(4), RADDR3 => RADDR(3), RADDR2 => RADDR(2),
RADDR1 => RADDR(1), RADDR0 => RADDR(0), DI8 => DI(8), DI7 => DI(7), DI6 => DI(6),
DI5 => DI(5), DI4 => DI(4), DI3 => DI(3), DI2 => DI(2), DI1 => DI(1),
DI0 => DI(0), WRB => WRB, RDB => RDB, WBLKB => VSS, RBLKB => VSS, PARODD => VSS, DIS => VSS);
M1 : RAM256x9SST port map(RCLKS => RCLOCK, WCLKS => WCLOCK, DO8 => n4, DO7 => n5, DO6 => DO(15), DO5 => DO(14),
DO4 => DO(13), DO3 => DO(12), DO2 => DO(11), DO1 => DO(10), DO0 => DO(9),
DOS => n6, WPE => n7, RPE => n8, WADDR7 => WADDR(7), WADDR6 => WADDR(6), WADDR5 => WADDR(5),
WADDR4 => WADDR(4), WADDR3 => WADDR(3), WADDR2 => WADDR(2), WADDR1 => WADDR(1),
WADDR0 => WADDR(0), RADDR7 => RADDR(7), RADDR6 => RADDR(6), RADDR5 => RADDR(5),
RADDR4 => RADDR(4), RADDR3 => RADDR(3), RADDR2 => RADDR(2), RADDR1 => RADDR(1),
RADDR0 => RADDR(0), DI8 => VSS, DI7 => VSS, DI6 => DI(15), DI5 => DI(14), DI4 => DI(13),
DI3 => DI(12), DI2 => DI(11), DI1 => DI(10), DI0 => DI(9), WRB => WRB, RDB => RDB,
WBLKB => VSS, RBLKB => VSS, PARODD => VSS, DIS => VSS);

end STRUCT_ram;

• У тебя какой SP? — KA   (15.07.2003 14:16, пустое)
• попробуй это — KA   (15.07.2003 14:15, 4203 байт)
  • Спасибо, помогло, но вопрос остался(+) — miki   (15.07.2003 14:45, 292 байт)