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module main (reset, data, clk, load, din);
input clk, load, reset;
input [23:0] din;
output [23:0] data;
reg [23:0] data;
always @(posedge clk or posedge reset)
begin
if (reset) data <= 23'b0;
else if (load) data <= din;
else data <= data-23'b1;
end
endmodule
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