Отправлено Victor® 19 февраля 2003 г. 09:35 В ответ на: Ответ: Да, не быстро. Спасибо, за инфу.(-) отправлено laso 18 февраля 2003 г. 19:17

------------------ Отчет Synplify Pro 7.2 ----------------
mul16|CLK 92.0 MHz

Design view:work.mul16(behave)
Selecting part ep1k10tc144-1

Total LUTs: 386 of 576 (67%)
Logic resources: 386 LCs of 576 (67%)
Number of Nets: 851
Number of Inputs: 2915
Register bits: 227 (227 using enable)
EABs: 0 (0% of 3)
I/O cells: 68

Details:
Cells in logic mode: 165
Cells in arith mode: 197
Cells in cascade mode: 0
Cells in counter mode: 0
DFFs with no input combinational logic: 24 (uses cell for routing)
LUTs driving both DFF and logic: 21

-------------------------- Отчет MAX+PLUS 10.2 ---------------------
Current fmax is 107.52 MHz

Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 62/86 ( 72%)
Total logic cells used: 572/576 ( 99%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.39/4 ( 59%)
Total fan-in: 1372/2304 ( 59%)

Total input pins required: 36
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 6
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 572
Total flipflops required: 221
Total packed registers required: 0
Total logic cells in carry chains: 203
Total number of carry chains: 11
Total number of carry chains of length 1-8 : 0
Total number of carry chains of length 9-16: 3
Total number of carry chains of length 17-24: 7
Total number of carry chains of length 25-32: 1
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0

Synthesized logic cells: 0/ 576 ( 0%)

-------------------------- Design file -----------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity mul16 is
port
(
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0);
CLK : in std_logic;
nRESET : in std_logic;
ENA : in std_logic;
nOE : in std_logic;
MUL : out std_logic_vector (31 downto 0)
);
end mul16;

architecture behave of mul16 is
signal A_REG : std_logic_vector (15 downto 0);
signal B_REG : std_logic_vector (15 downto 0);
signal MUL_REG : std_logic_vector (31 downto 0);

begin

-- Registered A and B values
process (CLK, nRESET)
begin
if (nRESET = '0') then
A_REG <= (others => '0');
B_REG <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (ENA = '1') then
A_REG <= A;
B_REG <= B;
end if;
end if;
end process;

-- Multiplication of registered A and B values
process (CLK, nRESET)
begin
if (nRESET = '0') then
MUL_REG <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (ENA = '1') then
MUL_REG <= A_REG * B_REG;
end if;
end if;
end process;

-- Tri-State MUL output description
process (MUL_REG, nOE)
begin
if (nOE = '0') then
MUL <= MUL_REG;
else
MUL <= (others => 'Z');
end if;
end process;
end behave;