Отправлено Recipe 04 ноября 2002 г. 09:03

Имеется такой код

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.all;

entity ADC is
generic (N: natural := 11);
Port (
DB : inout std_logic_vector(11 downto 0);
T_DRDV : out std_logic;
T_BEn : in std_logic_vector(3 downto 0);
RESET : in std_logic;
CLK : in std_logic;
BARHIT : in std_logic;
ADi : in std_logic_vector(31 downto 0);
ADr : in std_logic_vector(31 downto 0);
ADo : out std_logic_vector(31 downto 0);
RD : in std_logic;
WE : in std_logic;
EOC : in std_logic;
RD_ADC : out std_logic;
WE_ADC : out std_logic;
INT : out std_logic;
CS : out std_logic
);
end ADC;

architecture Behavioral of ADC is
constant Zero : std_logic_vector(11 downto 0):= "000000000000";
constant HI : std_logic_vector(31 downto 0):= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
constant HI_11 : std_logic_vector(11 downto 0):= "ZZZZZZZZZZZZ";

signal Sel_Reg, Sel_Reg_int : std_logic;
signal WE_Reg, WE_reg_int : std_logic;
signal RD_Reg : std_logic;
signal IO_area : std_logic;
signal User_Int, Int_Start, Sel_Int_Start, Sel_Int_Status :std_logic;
signal DBi : STD_LOGIC_VECTOR(11 downto 0);
signal DBo : STD_LOGIC_VECTOR(11 downto 0);

component IOBUF_pci33_3
port (I, T: in std_logic;
O: out std_logic;
IO: inout std_logic);
end component;

begin
T_DRDV <= BARHIT;

-- Adress area for interrupt
IO_area <= '1' when ADR(6 downto 5)="00" else '0';

Sel_Int_Start <= '1' when ADR(4 downto 2)="010" else '0'; -- 500' 32
Sel_Int_Status <= '1' when ADR(4 downto 2)="011" else '0'; -- 505' 32

-- Adress area for input/output
Sel_Reg <= '1' when (BARHIT='1' and ADR(3 downto 2)= "01") else '0';
WE_Reg <= '1' when (Sel_Reg='1' and WE='1') else '0';
RD_Reg <= '1' when (Sel_Reg='1' and RD='1') else '0';

process(ADi,T_BEn,CLK,RESET)
begin
if RESET = '1' then
Ado <= HI;
DB <= Zero;
CS <= '1';
RD_ADC <= '1';
WE_adc <= '1';
elsif (CLK'event and CLK='1')then
if WE_Reg='1' then
CS <= '0';
WE_adc <= '0';
if T_BEn(0) = '0' then
DBi(7 downto 0) <= ADI(7 downto 0);
end if;
else
WE_adc <= '1';
CS <= '1';
end if;
end if;
end process;

process(EOC)
begin
if (EOC'event and EOC='0') then
Int <= '0';
CS <= '0';
RD_ADC <= '0';
if RD_Reg='1' then
ADo(11 downto 0) <= DBo(11 downto 0);
else
ADo(11 downto 0) <= HI_11;
Int <= '1';
CS <= '1';
RD_ADC <= '1';
end if;
end if;
end process;

t: for I in 0 to N generate
U1: IOBUF_pci33_3 port map (I => DBi(I), T => not WE_Reg,
O => DBo(I), IO => DB(I));
end generate t;

end Behavioral;

После компиляции выдается ошибка не могу понять в чем причина может кто объяснит?

WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block .
This instance will be removed from the design along with all underlying logic
WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic
WARNING:Xst:529 - Sources are: XST_GND:G, u10:io, u11:io, u12:io
WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic
WARNING:Xst:529 - Sources are: XST_VCC:P, u13:io, u14:io, u15:io, u16:io, u17:io, u18:io, u19:io, u110:io, u111:io
ERROR:Xst:415 - Synthesis failed