Отправлено dsmv 25 октября 2002 г. 18:30 В ответ на: Помогите разобраться... отправлено Elresearch 25 октября 2002 г. 13:03

--
-- cntdec.vhd
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cntdec is
port( reset: in std_logic;
clk: in std_logic;
ce: in std_logic;
cin: in std_logic;
cout: out std_logic;
q: out std_logic_vector( 3 downto 0 )
);
end cntdec;

architecture cntdec_1 of cntdec is

signal d: unsigned( 3 downto 0 );
signal full: std_logic;
begin

pr_cnt: process( reset, clk ) begin
if( reset='0' ) then
d<="0000";
elsif( rising_edge( clk ) ) then
if( ce='1' and cin='1' ) then
if( full='1' ) then
d<="0000";
else
d<=d+1;
end if;
end if;
end if;
end process;

full<='1' when d(3)='1' and d(2)='0' and d(1)='0' and d(0)='1' else '0';

q<=conv_std_logic_vector( d, 4 );
cout<=full and cin;

end cntdec_1;

library ieee;
use ieee.std_logic_1164.all;

entity DB_count is
port (
CLK: in STD_LOGIC;
CLR: in STD_LOGIC;
CE: in STD_LOGIC;
-- FL: in STD_LOGIC;
-- CTR: in STD_LOGIC;
-- OP_MODE: in INTEGER range 0 to 3;
-- FLAG1: inout STD_LOGIC;
D_OUT: out STD_LOGIC_VECTOR(11 downto 0)
);
end DB_count;

architecture db_count_1 of DB_count is

component cntdec is
port( reset: in std_logic;
clk: in std_logic;
ce: in std_logic;
cin: in std_logic;
cout: out std_logic;
q: out std_logic_vector( 3 downto 0 )
);
end component;

signal cin0, cin1, cin2, cout2: std_logic;

begin

cin0<='1';
cnt1: cntdec port map ( clr, clk, ce, cin0, cin1, d_out( 3 downto 0 ) );
cnt2: cntdec port map ( clr, clk, ce, cin1, cin2, d_out( 7 downto 4 ) );
cnt3: cntdec port map ( clr, clk, ce, cin2, cout2, d_out( 11 downto 8 ) );

end db_count_1;