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а ASPEC Design Verifier - всякие там задержки проверять - в комплекте там свои либы для симуляции) надо загрузить готовый нетлист после синтеза с использованием их либов. Именно либов для синтеза.
Я хотел было прикрутить прилагаемы либы для синтеза (там четыре файла .scr .set .sdb и .db) к чему-либо другому типа леонардо или синплифи, но обломс полный.
Или я вообще всё не так понимаю? В первый раз все-таки....
Вот что это за ASPEC
ADVER (ASPEC Design VERifier) is a multi-function front and back-end engineering utility program for reading netlists, calculating delays, translating netlists to different formats, checking logic design rules, generating reports and more. ADVER generates output delay files for back-annotation and SPICE files for Layout versus Schematic check.
For pre-layout delay calculation without floorplanning, ADVER uses ctual gate delays plus estimated wire routing and capacitance for the chosen masterslice. For pre-layout delay calculation with floorplanning, ADVER accepts the wire capacitance and wire delay files generated by the floorplanning tool. For post-layout delay calculation, ADVER uses actual gate delays and the wire capacitance and wire delay files generated by the place & route tool. The program calculates delay timings into output file formats that match the user’s simulation tool (standard delay .sdf, VIEW logic .dtb or Mentor .dly format). ADVER can be used for both standard cell and gate array designs. Beginning with version 2.9, ADVER supports local scaling in delay calculation.
ADVER reads VERILOG, EDIF, NDL, DEF and GDT netlist formats and writes
netlists in VERILOG, SDL NDL, HSPICE, EDIF and DEF formats. Post-layout delay calculation can incorporate clock tree synthesis output. ADVER generates a report file containing design statistics and lists design rule check violations in error and warning files.
E-mail: 
info@telesys.ru
