--
-- f_out = f_in * k/m (наверное нужно - 2k < m)
--
-- по умолчанию f_out = f_in * 5/13
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith .all;
use IEEE.STD_LOGIC_unsigned .all;

entity clk_d is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
load : in STD_LOGIC;
m : in STD_LOGIC_VECTOR(7 downto 0);
k : in STD_LOGIC_VECTOR(7 downto 0);
clk_out : out STD_LOGIC
);
end clk_d;

architecture clk_d of clk_d is
signal cnt,sm,rg_m,rg_k : STD_LOGIC_VECTOR(8 downto 0);
begin
process(clk,rst)
begin
if rst = '1' then
rg_m <= "000011010";
rg_k <= "000001010";
cnt <= (others => '0');
elsif clk = '1' and clk'event then
if load = '1' then
rg_m <= (m & '0');
rg_k <= (k & '0');
end if;
if sm(8) = '0' then cnt <= sm;
else cnt <= cnt + rg_k;
end if;
end if;
end process;
sm <= cnt - rg_m + rg_k;
clk_out <= '0' when cnt < ext(rg_m(8 downto 1),9) else '1';

end clk_d;