module top (
inout  [63:0] sdram_dq;	
wire [63:0] sdram_dq, sdram_dq_o, sdram_dq_oe;

bufif0 sdram_dq_buf [63:0] (sdram_dq, sdram_dq_o, sdram_dq_oe);

memory_hub memory_hub_insertion (.sdram_dq_i(sdram_dq),.sdram_dq_o(sdram_dq_o),.sdram_dq_oe(sdram_dq_oe));

.....

entity memory_hub is  port(
		 sdram_dq_i :  in std_logic_vector(63 downto 0);
		 sdram_dq_o : out std_logic_vector(63 downto 0);		 sdram_dq_oe: out std_logic_vector(63 downto 0);

signal sdram_dq_out :    std_logic_vector(63 downto 0);
signal sdram_dq_en : std_logic_vector(63 downto 0);
attribute syn_keep of sdram_dq_en : signal is true; 
attribute syn_keep of precharge_enable : signal is true; 
attribute xc_props of sdram_dq_en  : signal is "IOB=TRUE";
attribute xc_props of sdram_dq_out : signal is "IOB=TRUE";	

.................................
sdram_dq_o  <= sdram_dq_out;
sdram_dq_oe <= sdram_dq_en;
process (wb_clk)
begin
	if (wb_clk'event and wb_clk = '1') then
		if cmd_write then
			sdram_dq_out <= sdram_di;
			precharge_enable <= false;
			sdram_dq_en <= (others => '0');
		else
			sdram_dq_out <= sdram_dq_out;
			sdram_dq_en <= (others => '1');
			precharge_enable <= true;
		end if;
	end if;
end process;

  Maximum Data Path: memory_hub_insertion/precharge_enable to sdram_dq[53]
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y21.YQ      Tcko                  0.419   sdram_dq_oe[0]
                                                       memory_hub_insertion/precharge_enable
    L29.T1               net (fanout=68)       6.130   sdram_dq_oe[0]
    L29.PAD              Tiotp                 3.028   sdram_dq[53]
                                                       sdram_dq_iobuf[53]/OBUFT
                                                       sdram_dq[53]
    -------------------------------------------------  ---------------------------
    Total                                      9.577ns (3.447ns logic, 6.130ns route)
                                                       (36.0% logic, 64.0% route)