//--input section-- reg [w-1:0]reg_data_in; always @ (posedge rst, posedge clk) begin if (rst) reg_data_in=0; else if (data_clk) reg_data_in=data_in; end //-----------------
//--output section-- reg [2*w-1:0]reg_data_out; always @ (posedge rst, posedge clk) begin if (rst) reg_data_out=0; else if (data_clk) reg_data_out=reg_data_in*reg_data_in+reg_data_out; end //------------------