module test1(in, out, clock, control);
parameter width = 8;
parameter depth = 16;
input [depth-1:0] in;
output [width-1:0] out;
input clock, control;
reg [width-1:0] shr [depth-1:0];
integer i;
always @(posedge clock) begin
  if (control) shr[0] <= { shr[0][width-2:0], in[0] };
  for (i=1; i < depth; i=i+1)
    shr[i] <= control ? { shr[i][width-2:0], in[i] } : shr[i-1];
end
assign out = shr[depth-1];
endmodule