module test1(in, out, clock, control);parameter width = 8;
parameter depth = 16;
input [depth-1:0] in;
output [width-1:0] out;
input clock, control;
reg [width-1:0] shr [depth-1:0];
integer i,j;
always @(posedge clock)
if (control) // shift data from in
for (i=0; i < depth; i=i+1)
shr[i] <= { shr[i][width-2:0], in[i] };
else
for (j=0; j < depth-1; j=j+1)
shr[j+1] <= shr[j];
assign out = shr[depth-1];
endmodule