module ram(clk, WE, addr, data_in, data_out);
parameter n = 8;
parameter a = 3;
parameter w = 4;
input clk, WE;
input [a-1:0] addr;
input [w-1:0] data_in;
output [w-1:0] data_out;
reg [w-1:0] data_out;
reg [w-1:0] ram_data [n-1:0]; always @(posedge clk)
if (WE) ram_data[addr] <= data_in;
else data_out <= ram_data[addr];
endmodule